<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/94187>94187</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
Vector register not reloaded from clobbered memory
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
vahur
</td>
</tr>
</table>
<pre>
Here's a snippet from c.zig which is included in the attached .zip and should print `foobarbaz` in the output, but writes `baz` instead (plus some random chars, but these can be ignored).
```zig
pub fn xmain() void {
var s1: [9:0]u8 = undefined;
s1[0] = 0;
_ = strcat(&s1, "foo");
_ = strcat(&s1, "bar");
_ = strcat(&s1, "baz");
var out = std.io.getStdOut();
_ = out.write(&s1) catch unreachable;
}
```
[src-ir.zip](https://github.com/user-attachments/files/15529033/src-ir.zip)
Attached is the unoptimized LLVM IR generated from c.zig by Zig compiler and optimized LLVM IR produced by running LLVM 19's opt:
```
/usr/local/opt/llvm-19/bin/opt -S -o c-opt19.ll -O2 c-unopt.ll
```
Line 282 in optimized IR is causing the issue. It is reusing previously loaded vector contents even though memory from where it should be loaded, has changed.
```
line 190: define internal fastcc void @c.xmain() unnamed_addr #3 !dbg !644 {
line 198: %0 = alloca [10 x i8], align 16 ; s1
line 210: %1 = load <16 x i8>, ptr %0, align 16, !dbg !660
line 217: strlen.exit.thread: ; preds = %Entry
line 229: %endptr56 = getelementptr inbounds i8, ptr %0, i64 %7, !dbg !672
line 230: store i32 7303014, ptr %endptr56, align 1, !dbg !672 ; <- This changes %0 contents
line 239: br label %Then1.i.i23, !dbg !681
line 218: Then1.i.i23: ; preds = %simd.firstTrue__anon_1647.exit23.i.i, %strlen.exit.thread
line 219: %18 = phi <16 x i8> [ %.pre, %simd.firstTrue__anon_1647.exit23.i.i ], [ %1, %strlen.exit.thread ], !dbg !697
```
The second argument to phi on line 219 `[ %1, %strlen.exit.thread ]` is the problematic reuse.
It should load %18 from memory since memory was changed by store on line 230.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUVltv2zwS_TX0y8CCRN2sBz_kUmMDdFGgDfqwLwEljiUuaFLgxWny6xdD2bGTZot-QWBH4lzODM-ZifBejQZxy-pbVt-vRAyTddujmKJb9Va-bP-FDhlvPQjwRs0zBtg7e4Ahe1UjPE9qmEB5UGbQUaIEZSBMCCIEMUwoIXtVMwgjwU82agmzUyYAa_K9tb1wvXhlTX72sjHMMTB-B30M8OxUQE-2b1Y-oJDA-GbW0YO3BwQnjCQ8k3D-7Bkm9AiDMNAjqNFYh5LxLmP5PctvTp9Nvvy-qnF5M8ce9gZ-HYQyjG8Y7-BolQTW3i4GAABH4cAXrLwBVt92rLzJWX0fN8DKe4hG4l4ZlKy8vU5Ffr5g9S3ZJsv8zYLOntI7H9wgQkrc-IJKYZzvrWWcM979rUMv3D91eP3g8L5YG8PJWWbKZiOGH0F-i0uYz7LYGLJ0dZdEHQwiDBNE41AMk-g1XrK19x8u5PRY33o3rJUjBrH6nvHNFMLsWXnD-I7x3ajCFPtssAfGd9GjWy-kO6AJnvHdXmmk76KueZeXJeO7q4C8uy725kxX5RMRo7FzUAf1ihK-fv35b3j4DiMadCKgvBZA_wL_USMM9jArjS4x_XfX2VkZB5Rk7qIxyozLWdElbdk5UFmftoFqc4zvtB2EZnxHtnyn9fGwJu9dT2Slt7D-AWsLw9rOoegyrWH9jcOwTrVkWn8ePn1-VQaBbzjp8IL-4Tu1YxDRE15qi_I-YgYPgQ4cLgezw6Oy0esX0FbQDDjiEKyDwZpAdwF4RNK3jeMEBzxY97K08HlCh6DCeTb0eIpA1JyEJ1GbEWX2KXRNoIsuJy0uugNlAjojNOyFD8Nwkm-VD9m1qKMx4oDySUjpgPGyBMYL2Y_01VTVRe-nDJukdl7nid5C002Q-oscfoHaJG7egdBqNFA0JARW3pLgL0F4kZ-CFCkIlQmsvCuaJUT5hULMwaU81-EWlb7Be1c8L1qK6oPTaDL8pUIWJodC0ts__xDC2aH0CQ7j9RcT3Mt1bNJ2QoxGzsHVTbIcMaBGkhiBVaa30UhPJXzAr5qK_m4_4G_5dY4yX_BbokHJoS3zMi-qq1jn5Fct-S3iW0GsvFvD46TOxPHLrZ15-C5zqq53oEWPmuweJzRFpjLFyw8ZNu9vMtHh2pra9LGdXh1ktlfOh0cX8elJGGueiqZq0zXxklyXNPUn13edLgFNzFmWzDyp98whKtJ5NtOmvvvb7HDi7cm7-L9o3gwvHenaPwyTxwnB42CNBOHGSFyBYBNua-BcFa31v0tNi3-ZyrOzvcaDCGpI0wdPg-HhbYIsukq9ShPmNG28MgOeH54vg4Xm8cK-N2Rlnq3ktpRd2YkVbou2aMuubIpuNW1F0_F9iVVTDaKsB1G3fYNN2-5lU5e92KzUlue8ypu8zOuqqbus6qt9udnse5F3Q9_vWZXjQSid0fzOrBtXaaRuu6rYtKvERZ_-F-Pc4PMyb2k71_crt00zv4-jZ1WulQ_-EiWooHH7c5m7DkflAzowNoDD01Belpa2fY8O5akZq-j09g9rlRKct83s7H9xoOWTYNFqXWAft_x_AQAA__8OUAg2">