<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/92875>92875</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Line-level debug information lost during ARM instruction selection
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          orf
      </td>
    </tr>
</table>

<pre>
    The following Rust code produces three assembly instructions when compiled with optimizations:

```rust
pub fn add(left: usize, right: usize) -> usize {
    let result = left + right;
    if result < 10 {
        return 3;
    }
    return result
}
```

```asm
add x9, x1, x0
        mov w8, #3
        cmp x9, #10
        csel x0, x8, x9, lo
        ret
```

However, line-level DWARF information is lost for the if condition, despite it fairly obviously mapping to the “cmp” and “csel” instructions.

compiler explorer links:
- [Rust](https://godbolt.org/z/Y9K5YKfKd)
- [llvm IR](https://godbolt.org/z/6vEqze6f3)

It seems that in the “AArch64 Instruction Selection” pass, the conditional is lowered to:

```
3:gpr64 = SUBSXri %2:gpr64common, 10, 0, implicit-def $nzcv, debug-location !21; example.rs:0
%4:gpr32 = MOVi32imm 3
%5:gpr64 = SUBREG_TO_REG 0, killed %4:gpr32, %subreg.sub_32
%6:gpr64 = CSELXr killed %5:gpr64, %2:gpr64common, 3, implicit $nzcv, debug-location !21; example.rs:0
```

which as I understand it, is “subtract 10 from the value, and select based on a flag indicating if the result is 0”.

At some point later, this is optimized to a simple comparison, but the line-level information is lost.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJycVVtv4zYT_TX0y8CGTFq-POjBju39guxiAWe_dvcpoMSRxC4lqrzYSX59QcoXeZEWRYOAljhzDmeGZ0bcWlm1iBlJNyTdjrh3tTaZNuUo1-It-1YjlFopfZJtBQdvHRRaIHRGC1-gBVcbRODWYpOrN5CtdcYXTurWwqnGFgrddFKhgJN0NejOyUa-8-hA2JokW5Jc1nnS_xtvXb_V-RzKFrgQhC4Vlo6wNXgr35HQBzCyqoc7KxgTtuvfgCw2PQcAgEIHBq1XDgjbQmACQjcXhoGnLG-ODzBN7nnCn0HnTQvsDkYW29vL2aPnOed2sV-T_DBzbpt-hwsBr6uQ5Os0rlf_VaOPcFqGTUIZu24XTXdGEMqmN_fCogrwQBJRvZPSVw-D7h9i-58-4RFNxMgWxwqPqGD7-_qwB9mW2jTxMkFaUNo6KLUBV2MoZKFbIYMxgAXaTjoE6aDk0qg30PlRam_VGzS864K-nI5QsqNkmZDVQ9F0l-ct8FYMLBbVzTRU3WQY_Fl8BvC1U9qgCTn8vAlvDCTdBFWTdEvosnaui0a6J3RfaZFr5SbaVITu3wnd_1g9pT-eyidB6GpAoNSxgcfDv-OYH3d_vuO8ZFeOfn10YBGb0FHcgWzvK7Fem6Kez-Dxlik8o8L4dCtEx60NxQ7Ya_W56i_nhAYFOP13bde_MsLWVWfms9gpz__fPH83EghN6cVQ6Kbp73QaZRUX2XRKFtKNBZZA6Kx9L479tee-Gitd9CohdEqnhG0AX3nTKZyYUKuL4Gg66w9hNJ7-5etvklHZNMCuHumv8R12n16-fX057D71kfyUKoybIVnfFan1ucFqYn3-wuiVcH5H-PC8-_zdDEiu551JPigDGxbgPyf_UfOdalnUwC08gm8FGutCF0gXD7Q3eVifO8MLFwZWaXQTBXDkysc5GTA2igVyblGAboFDqXgFshUyRNdWoWED6jz9pIXkqqu7nlo7sLpB6LRsHSju-uHgamkD6jzho9KAgw11wfgV4EbavmC5d_GswUD5YJRMRiJjYsVWfITZdDGd08WSLpajOpslaZnnrEjns4LnyWJFk1IsVozyaS5wORvJjCZ0lqR0mizSRbqcsPl8ztNkSZGyaTqjZJZgw6WahN4N3TmS1nrMVnS5SEeK56hs_CZS2uIJopFQGj6RJguYce4rS2aJktbZG4uTTmH2-ZZXlMBddnFKCm9CzdeHL8Phdb4lqduRNyr7ZZRIV_t8UuiG0H048Pwz7oz-AwtH6D6GaQndxzT-CgAA__9m8l0s">