<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/92772>92772</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV][Vector] Generating `vsetvl` LMUL=1/8 for zve32* extension might be illegal
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          SharzyL
      </td>
    </tr>
</table>

<pre>
    ## `vill` might be set when LMUL=1/8 with zve32*

RISCV Vector extension includes a series of zve32* extension for embedded processors that supports a maximum EEW of 32 (instead of 64 for standard Vector extension).

For zve32* architectures, `vsetvl` instruction that sets LMUL=1/8 might be illegal, as described in riscv-v-spec 1.0 document (Section 3.4.2):

> When LMUL < SEW_MIN/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. For example, with VLEN=ELEN=32, and SEW_MIN=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.

> The use of vtype encodings with LMUL < SEW_MIN/ELEN is reserved, but implementations can set vill if they do not support these congurations.

Also we can find in the implementation of Spike, `vill` is set when seeing `vsew > vflmul * ELEN`.

https://github.com/riscv-software-src/riscv-isa-sim/blob/c81d8e73daf1875d79a54f28f67df150fba0e44c/riscv/vector_unit.cc#L42

```cpp
 vill = !(vflmul >= 0.125 && vflmul <= 8)
           || vsew > std::min(vflmul, 1.0f) * ELEN
           || (newType >> 8) != 0;
```

In conclusion, setting LMUL=1/8 might cause `vill` being set in some zve32* implementations, crashing all subsequent vector instructions.

## Miscompilation with LLVM/clang

LLVM/clang is not aware of this problem currently. It will generate vsetvl instruction with LMUL=1/8 with `-march=rv32gcv_zve32x`. The following is a minimum example:

```c
void foo(unsigned char *restrict d, unsigned char const *restrict s) {
    *d++ = *s++;
    *d++ = *s++;
}
```

When compiling with `-march=rv32gcv_zve32x -O3`, it generates
```asm
foo:                                    # @foo
 vsetivli        zero, 2, e8, mf8, ta, ma   # <- setting mf8 might cause problems!
        vle8.v  v8, (a1)
        vse8.v  v8, (a0)
 ret
```

https://godbolt.org/z/j85n9Pchv is an interactive playground for above code. It could be noticed that gcc generated the same code.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyMVltv47oR_jX0y8CGRPkiP_gh8aVYIHtaNKfZxwVFjiSeUqRLUvImv74YyvHtdLfHCCKIIofffPPNRYSgG4u4YYtntthNRB9b5zevrfAf7y-Tyqn3DeMF4wWwZTZoY9gyg043bYQKIWCEU4sWXr7-64UVu5zxQwknHVv4GLDgjD-xbMey8_9_fnndvsEbyug84I-INmhnQVtpeoUBBAT0GgO4-nL-Zl9Np7oKlUIFR-8khuB8gNiKCKE_Hp2PZKQTP3TXd7DffyNLBQfGS21DRKFoYTlPpkIUVgmv_gSI8fXsFvbB-Ssc4WWrI8rYewyMbxMvAeOQmKFbfC8jwR1hYQz37FzI08ZgIwzZEAEUBul1hQq0Ba-DHKbDNBxRQj7LQDnZd2gjefKKo_1iNp9xxtesuCOZFXv49hkTYMUWXvffvn_98hvjh_3L_je6L7boEXQA66DphRc2IoKwoLujQbpIpCtOrjcKWjEgoHV900KlYyCEsUWovUhIhIFhpNBjo0NED9FBiM4jiAgGRYjgLAKOts8evxGYYkeYCIqAQRitHiHI1mmJMzikCAn6SOeTxm4ssGJH8dmCsOricLErx6WRC1fDWaDJLWfNO8lo0Aqhdr0fnXN1gi4aJD_Fo2uzR65_bxH6gHRuiO9HYko6pW0TRpA_CQO57DGgH1ARyKqPD64HkMKmFKO8A10T6e-gHFh30TutBQTpbNP78dgdwicTHJwwmaq1VZ-xe2DZ1fB61P_GT0GfE12Ha4oHRG2bs9xPQK4Ptel6A5QWKQbL7O7uNsZjIHXyA-OHRse2r2bSdYwfRoEHV8eT8DgNXl4WdRDToGlTZVzF-EGWuSpxVShR5-VqoVZrsZjXvKyXK1Xni6yuRIbz-cUC44cxZt97q-NMSsaLlzm_i9syG__k8TiujByzYgeM54yXn64Ve1rLZjlfAONLxpcXr4stfSopA0cT1x9bbdlqCxeiQlTEQ_HUaXsxTlzns6xmfH2l8CeWGC8tnn4neSVI-3RvwkrwWPH84Nitt18s6UOafixuW4pppFj-j7okBWn5RgJVijqpQFsIrsNrKXyQK1mWXoSWDghjIPRVwP_0VLbOSXRTHu9leu4xX3WQrjtqcy4_KX9e3r6SCoywze2R2_WxlEUQpCYSc2x1oNyuDHYge-_RRvM-gy8RThToBi16ERHG0n1Xty9Ze9_Q2DKbdlT9WbHzQ8EbOXxPVPwg3acyUDtj3EmPeAR02qY-9Fm2Hur0RYPj--C0gto5xsvepq6sQLbCkzY8hui1jJBKxf1n6WyId5tCksbq-Somxp8U48-MP58l_hTG14tw_touttr9Qmep64zxIw7-D2sw_XtBBvgWdLwEJDzYF6EbV4iZ4jYzfvpLw8o8owPn1A4Y9WD054YP9I6uTf0CU4vo6vSIIr2ITyvFdnpJlq6-z5GzugLl4F3WDgbL2QAwJJOMlyL_U40YwuOe7LrHY_wFyw9V1anKmThzvmH88MH44Y9yYdf_kO2QREjTVcTUqAeEoxHvjXe9VWkCEpUbqHcoTJkhU1uskFJJS1TjBNNIeYmOSr0jiO58aqI2hVoXazHBTb7Klzxfl9lq0m7mSi6FXGW4EPMC52uZZ9W6XOMql0W9UOuJ3vCMz7MFz_LFvOCLWc1zWc15KVbFWpTLgs0z7IQ2M2OGjtyb6BB63Kz5asUnRlRoQppaObd4gvSRcU5DrN_QmWnVN4HNM6NDDFcrUUeTxt00jLLFji2exwGQLXbwt9HRa6M7z3V35aC-nQev4-njYDfpvdn8ogcSpPNjevTuD5SR8UNyJDB-SI7-NwAA__95oZDt">