<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/90892>90892</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISC-V] Miscompile with rv64gcv_zvl256b
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          patrick-rivos
      </td>
    </tr>
</table>

<pre>
    Testcase:
```c
unsigned int a;
int c = 1;
unsigned short d[200];
signed char e[400];
int k;
int main()
{
        for (long h = 0; h < 20; ++h)
                d[h] = 0x8000; // 16th bit is set
        for (long i = 20; i < 40; ++i)
 e[i] = 0;
        for (short j = 0; j < 20; j += c)
 {
                k = -((int) d[j]);
                k = ~k;
 k = (unsigned short)(e[0] > k ? (signed char)(j * 20) : k);
 a = a > k ? a : k;
        }
 __builtin_printf("%u\n", a);
        return 0;
}
```

Commands:
```bash
> /scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang -march=rv64gcv_zvl256b -flto -O3 -fwrapv red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 red.out
65440
> /scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 red.out
32767
```

Reduced LLVM IR:
```llvm ir
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

@d = global [200 x i16] zeroinitializer
@.str = constant [4 x i8] c"%u\0A\00"

define i32 @main() #0 {
entry:
  store <16 x i16> <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>, ptr @d, align 32
  %0 = load i16, ptr @d, align 8
 %conv15.12 = zext i16 %0 to i32
  %not.12 = or i32 %conv15.12, 0
 %cmp17.not.12 = icmp sgt i32 %conv15.12, 0
  %1 = and i32 %not.12, 0
 %conv23.12 = select i1 %cmp17.not.12, i32 %1, i32 65520
  %conv15.13 = zext i16 0 to i32
  %not.13 = or i32 %conv15.13, 0
  %cmp17.not.13 = icmp sgt i32 0, 0
  %2 = and i32 %not.13, 0
  %conv23.13 = select i1 %cmp17.not.13, i32 %2, i32 0
  %cond29.12 = call i32 @llvm.umax.i32(i32 %conv23.12, i32 %conv23.13)
  %conv15.14 = zext i16 0 to i32
  %not.14 = or i32 %conv15.14, 0
  %cmp17.not.14 = icmp sgt i32 0, 0
  %3 = and i32 %not.14, 0
  %conv23.14 = select i1 %cmp17.not.14, i32 %3, i32 0
 %cond29.13 = call i32 @llvm.umax.i32(i32 %cond29.12, i32 %conv23.14)
 %conv15.15 = zext i16 0 to i32
  %not.15 = or i32 %conv15.15, 0
 %cmp17.not.15 = icmp sgt i32 0, 0
  %4 = and i32 %not.15, 0
 %conv23.15 = select i1 %cmp17.not.15, i32 %4, i32 0
  %cond29.14 = call i32 @llvm.umax.i32(i32 %cond29.13, i32 %conv23.15)
  %cond29.19 = call i32 @llvm.umax.i32(i32 %cond29.14, i32 32767)
  %call = tail call i32 (ptr, ...) @printf(ptr @.str, i32 %cond29.19)
  ret i32 0
}

declare i32 @printf(ptr, ...)

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #1

; uselistorder directives
uselistorder ptr @llvm.umax.i32, { 3, 2, 1, 0 }

attributes #0 = { "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zaamo,-experimental-zabha,-experimental-zalasr,-experimental-zalrsc,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-h,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smepmp,-ssaia,-ssccptr,-sscofpmf,-sscounterenw,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
```

Commands:
```bash
/scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang -Xclang -disable-llvm-passes red.ll -o baseline.out

/scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/opt -passes=slp-vectorizer red.ll > opt.bc
/scratch/tc-testing/tc-apr-29/build-rv64gcv/build-llvm-linux/bin/clang -Xclang -disable-llvm-passes opt.bc -o opt.out

QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 baseline.out
65520

QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 opt.out
32767
```

`-Wl,-opt-bisect-limit` points to SLPVectorizer, but extracting the IR that passes before/fails after causes alive2 to flag it as UB.

https://alive2.llvm.org/ce/z/JyXU8-

The input c file passes sanitizers and does not appear to have any UB, so this might be a different pass misbehaving here before it gets to SLPVectorizer.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzcWVtv4zba_jXKDSFDog6RL3KR2GOgH1p83Wmn27uAoiiLY4pUSEpxfLG_fcGDDj4kO110sGiDwHzel3xPDymSspFSdM8JeQiypyDb3qFeN0I-dEhLig-hpINQd6Wo3h5-JUpjpEiQPAbRNogegzxy_9jJPbeuKkC5BihInpzaSBgEyRbEk24aqhohNaiC7AlGUZBtpxG-HzdIAhJkT-l5t3F6OJNaRHkAiwCufXb3vhP4v1pIEMCCCb4Hjc0nCpInCzcAWhzApwA-NZMPcPFn8myCbOusj0UUebNdAHcgznUDSqoBVUAR_X50au1dSGrDp4vwdA5vCqdTvKncC5-Ow69zSV8XJX21XpMtwLPbK2rGv4P1EVoaC8p1ANe25q-Geri-SuDc7l_zhHhNAIvzmTZOYGHKilxZn-zInS1jnnE3zKT-aMqAaxAkj-BwlgKyEdDCB_KjLrMM7rde8fxc9pRpyp87SbmubaEwgFkfZBtu4QagW5VKonvJF3MwOZ2eAi_az41oW8Qrdf2slEg1XpV8MitHYYk0bgK40zjURGnK905AnQwNETuTdBXKIU_3eJhkxoY2ZJT3R6Myi3-HGeJ7ELZI4iZItt7i-TQwmOUlCGumBQj_PwFh_SpRNwBJqhUGobBA9HrO7B-ffvryvPn5i3cTwM3ACA-SLcxyIwTJVsueGEiO-ll1BAfJdohXUQA3p4EksJ6HnAaSp6P83xZtK3whbR9KqvCQp-dJ51maRt-Z2b8RXQm8z-8_WMGfSdVjUoEff_ztJ_DD5-uFbEgCVDqtRnJPNKiQRgy9iV77xx-SsA2SRxJ2QfKYp_YjpBOIYREkjzEsQp5Ap_slds_k0q2WtGNkdOnLCXt-4OKVu4kK97yfzPxnGlXWZs9EiRhwZww4AhrnZvM5ESkop5oiRk9ETkYrpaW1w4Irjbg2lqmxK4wZnneM6NF8RBdxK1JTTgBNIAjSaD6WQACTaN57CdfybaIVAKWFNDVu4tznaFZxsqFxDkIzW4XZnP5mUvLJKDpDeBpVdvdldM9BAkdaAphFdjaYQJWl5aZBMR5tMMOCD3G2iqE1O5GjthGtIy3MvCx8c6HHkUK6OVt4MP6jhee2i-9XCxOK2w6ovf7Q0HTE7rDi1TjSObn0L_gAk9G5Ioxgk_tlaMuhcxOPOM8yuAw4ZpKck_AeA8k7DCSXhSzySK4piC6Hw5t1X3v1hScfFp4sCp9IuHBTwfXIH0aMjU-h2axWfYuOK1M8LBZlWsIXnqdcFrfABSPptxGavkNo-gGh6TcQmtwk9NqrLyL9kNB0UXZySeiCz-QP8Okm4Aaf6eL-OfORfRud2Tt0Zu8_odk3sJneZPPKqa8g-5DMbFFz-tHqTP8om8kNNrOr1WmHrv-o7ylTdx84d2rcGH8aUbZwCotOS2O3Wq3suZZG03Xa78zmDD3P2qW3CCCJXlI036f9IYoZktMpuvQ_Rz477ZMnsOs51lRw8Ki1NHdvwIVJu0T4ALioJSGAC_XGMeCi56-UV8DcxHqGNCoZAa-UMX_Tb0kr5FsACy44mWJdpHWDXF-1P-_jyxR7RRg1R31FJKioJFjTgSj_Vrzs9ExehNiYCwSwK8JK9gCIwAV7SGtJy14T5S8d5uZ0b14wobtShTVBupdEmbtLsrVXmqc8LakO4CaAT8g12DWVa2rXtK6RhKGjg4NrThQrOcKacEyol9z9dsbHCedptcD1Ak9jWAyLchLMi8wkJHDGeWpwSOzHsSOStoRrxELVtl17Q8tvadVt7U3li1C0utb3NwafEGrFDW3ZoBtahiyPV2qp8LW6LuvWXDEv9RTXlHW39Upd67W6keDwnnfT8dra5BvzoRoseq6JJPzVyXukO-SgHhDzcFCzelBnHXog2NKpWkSdtiVda0tQalQpjN0eYKCou7Ye8Vl4pTTShPBRkBRrhzX27RR7EVn1eXpkFg6oIiPoHSiR9CrKB-SHcdQJ53roytaiIx4Q6z0q6QR0izjtvEjYq0ctwiMirUeKtjajo6oxQYp4POBuRDWXmNHuWL_Uk-q1RRi_vLyMihcjV6I6k1-E76c1NYVThZGsKmb3uVlfs141s1Y3BFUlWuBygdWMsVvoXhC8asUwK-qWtLQ6zoqxeCdcdpK2Q1TOCrN3z9JQOeaPg1mVHJloorO5nFAMC-lhno4IIw9aFNt9JDyhV9_piju5uk4lds3Bi4dRPrrW2WBng90gt4hOmLimdk0rOg_G1iZ9qih3vmrnpG584x-4Uz0OaJZg7KXY73gnikvRTqib0MkjjFqBRkzrETE1GmHpFtiJYu6erRM1XDrUUK65ZrPQoX4c33Tex1jkwX1y31S-Jb51JR5cjIPyDfHDlO92_LRt74IOfkoGPyeDZ2qYqRr8NA2HvW9HPccj8FGGA5_GuN3XotFeje1opyY7Ndr5PAef6MDiCPq5GFicJ8UkwCgtRmzfeEchjdb5iLMYjjDPsmTSF_HadMD5dD8_1-PpXP_zrjngT_he87t8p_m7byuqTA1uZIeUIsp-scUYCAUokblCcbL4cu575CQ6DXzwINkq1oUDwVpIeiJyzCZIPgHR6VWJ_1e0uOiGFoMuGPkrfGF5PZuLrzn-OmWcsf-fvncN8ij8p933RKfDkiqCdchoS3WQR6ATlGtlXpJ_-fHn36Y1Z14Cyl4DctQSYZMl0A0BP3wGukEa-PVQklqYC8yuRpQpgGpNJMBmM1cAMToQaBzXDO0B1QAp8OVptUyt0bqzT779uctZrOz7iZCGFnPu7U4B3P3f2-9finBp-mtDAOVdrwEGNWVkTEkhTrWpQNm38EoQBbjQAHUdQdKk06CBAMTfwJcnU6USQDdUgZbuGw1KAhCoaF2bi5-rE7RUlaRBgyGhIZL4sk1Je3KDu9Vd9ZBU62SN7shDfB-n-X2ep_ld81BAUqAc3ReYkDyBeVmXGSzwOs-jCGUY3tEHGME0yiIYr6Mky1cJTPA6TqrsvlrDPC-DNCItomxi6Y4q1ZOHdVSs4R1DJWHK_vAKISevwHaad7Fseycf7KNc9ntl3gKp0mr2oqlm9hfbzz_8sgl_C7It-IkqLNqO2u1dN-Dit5-7XrKH8wncU9305Qqbu8POuPZN2EnxlZjr8s4mpAK4swn_OwAA___4_9rW">