<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/90628>90628</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Allow RISC-V "V" instructions in inline assembly without having to add the RVV "V" extension to command line
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          johnplatts
      </td>
    </tr>
</table>

<pre>
    Here is a snippet of code that compiles successfully with GCC but fails to compile with Clang unless the `-march=rv32gcv1p0` or `-march=rv64gcv1p0` option is added to the command line:
```
#include <stddef.h>
#include <stdint.h>
#include <asm/hwcap.h>
#include <sys/auxv.h>

#ifndef COMPAT_HWCAP_ISA_V
#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif

bool IsRvv1_0Supported() {
  int64_t bits = 0;

  const unsigned long hw = getauxval(AT_HWCAP);

  if ((hw & COMPAT_HWCAP_ISA_V) == COMPAT_HWCAP_ISA_V) {
    size_t e8m1_vec_len;
#if __riscv_xlen == 64
    int64_t vtype_reg_val;
#else
    int32_t vtype_reg_val;
#endif

    // Check that a vuint8m1_t vector is at least 16 bytes and that tail
    // agnostic and mask agnostic mode are supported
    asm volatile(
 "vsetvli %0, zero, e8, m1, ta, ma\n\t"
        "csrr %1, vtype"
 : "=r"(e8m1_vec_len), "=r"(vtype_reg_val));

    // The RVV target is supported if the VILL bit of VTYPE (the MSB bit of
    // VTYPE) is not set and the length of a vuint8m1_t vector is at least 16
    // bytes
    if (vtype_reg_val >= 0 && e8m1_vec_len >= 16) {
      return true;
    }
  }

  return false;
}
```

We really want Clang to allow the above code to compile on RISC-V, even without specifying the -march=rv32gcv1p0 or -march=rv64gcv1p0 option (or another option that enables at least the RISC-V Zve32x extension), as the instructions in the inline assembly statement are only executed if the RISC-V "V" extension is present due to the check of the result returned by `getauxval(AT_HWCAP)`.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyEVtFu2zoPfhrlhmjhyImTXOSiTdZ_BTb8wzpkOOcmkG0m1iZLhkS7zZ7-gHLipGl7DhDYjkh-lMiPpFQIem8Rl2J6L6brkWqpcn75y1W2MYoojHJXHpaf0SPoAAqC1U2DBG4HhSsRqFIEhasbbTBAaIsCQ9i1xhzgWVMF_1utIG8JdkqbAOROur10ZZTdQ2sNhgBUIYgsuamVLyqRrn2Xyn3RjZtEZAk4fyXMJhfChrSzcYdliSX7YbTC1bWyJRhtUaR3IlmL5E5kyfHX_5WptoVpSwSRrgKVJe5uK5F--kCsLX0oVqEW8qF6LlTzMcQhCPmg2pfuUmVQ3NkSd7D6_9dvdz-2n3-u7r5tH5_utptBo8SdtviOBgg5H7MHka74W8jZRsgZ3ICQszshZ0Iu-HcCQlvq3aX73DkDj-F71423yVPbNM4TlhFpAWJ232sBaEvZZEuQawog0jUkIr2_BAIonA0ErY3kKsE4u4fqOSrvkfjwygg5Px2At3UNoXf9IeZsJ7P3QsLbStcM-oHwvGeAoP_glgDn9XjbYbE1aM8-OfCw3Xodim77YtCegLPJGeF07o4ODW497rd8igsMNAFfqafyX9WvE8BWQj4I-QCrCovffXEp6FptifdN0GFBzkeiExhUgWCcQX4gDMBMjxaktHmDqPbWBdJFVKtV-H1eqbmQlUcIQ9IHaxVq6JxRpA1yPnqBkLILSJ3RIOQ0EXIFf9A7fuOcn_WYn6TitxLTlRXTFQkpz8j93mQRvGeQaBBjddYSaXTF5c4vOX-VPabz6rX8dax7vl8Ta4jIjwrh-2YDpPweiWM6nJ_Zxw1k8_jlC_Oc293mx1_fPjEnWfD16f64_gY26jH9dADrCALSMTUIBu2eKkb776y-AY5ZvuBXLJBXJwZuKFyQXDFcNJfxOgnH2ZvaAPBIrbdAvsUhYNH1bH36M3yeFo42O8W0H6I8aF212fj8ieBRxeGgLB3bPzlQxrjnGCGVuw6Po-U8LJyF749Pq5tNZFiHNo4P1xKEBgu9O2jGqRDeGR48Od4ZG6eZIeTceVDWUYX-tBjLCK3KeagNOWEH_Tbg7w5T-QL4QmiDdicyqn6KaRvItwVDBdD2uMZTCFQIWOfmAIEUYY2WYuU5aw6AL1i0F-w7-hJSboSUZ2dMlMZjYOOyxWHaxZ7heluPoTV0zBGWkB94fH7UfLPkdlQu03KRLtQIl-PZeDJZZPPpdFQtS7nIssVkMZ1PlFpMZTaeZWoyT0tMZvkunYz0UiZykkzSZDxLZun0dppipvJZmo1TOZvnKCYJ1kqbW2O6-tb5_UiH0OJykWRyPjIqRxPiBURKi88QhVzP0_XIL9nmJm_3QUwSowOFMwppMvHmwoHaiOka7iKPruJ2nY3rTJyoVKlOH-lY9uXK3eFt9HteDheLUevNsiJqAl8xYqnuNVVtfls4vg7wdo-vm8a7X1iQkA_xkHwTiEH4JwAA__90J-LD">