<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/89971>89971</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AMDGPU inline assembly with s constraint incorrectly emits VGPR use
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/Yonee4P1G

```
define hidden i32 @test(i32 noundef %mask) local_unnamed_addr #0 {
entry:
 %tobool = icmp ne i32 %mask, 0
  %0 = tail call i64 @llvm.amdgcn.ballot.i64(i1 %tobool)
  %cmp = icmp eq i64 %0, 0
  %conv = zext i1 %cmp to i32
  %1 = tail call i32 asm sideeffect "s_mov_b32 $0, $1", "=s,s"(i32 %conv) #2
  ret i32 %1
}
```

This is incorrectly emitting a VGPR for the use operand  `s_mov_b32 s0, v0`


</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJxsU8GO2yAQ_Rp8GW0EYzuxDz5kN8qeKq2qtlJPETYTmy6GFHDa7NdX2NlmlVZC2Ixm3nvzBmQIurdEDSsfWbnL5BQH5xvpA9kxa526NEOMp8DyLcM9w33vVOtMXDnfM9y_Mdx_d5aoeBHPjO8Y3173Nb-u-ajoqC3BoJUiCzpHYAWPFCLDKp2sm6yiIzAsRxleGdZgXCfNYbJWjqQOUikPDHMObPO4YJKN_pJ0zadUGl3rnAGW70B34wksLVTvoE9wlQMpxufEKLWBThoDel0kVcacx5UcVd_ZVSuNcXGl10XSKW4cDOsPSInrLyn9XJCw5PeMnbPnOfGNfkdY8FJJdEnnh0RxLy1HkGGEoBXR8UhdBIYYDqM7H9q5w2ImY1gIhrj8Ist3geFTmCPV1YmkIdnL8MboKb4bJa7j2-z-O8dl_zLoAGnZznlPXTQXoFHHqG0PEr49v3yGo_MQB4IpELgTeWkVAFvzm-gwSz7fg2eqyVWd1zKjRmxEXlf5uubZ0OCa87KiFOF1Xq2LohM1lUqUAmXLi0w3yLHgBRaiyouSr0SO1YawxY5KITbECk6j1GY1z9j5PtMhTNRUdb0RmZEtmTA_BMRWdq9kFcu320-755evycNyl_kmlT60Ux_SVdEhhhtY1NFQs-SDtibdeBkCja25wC8dBwjQORuil9rGf9wLi3FToGzy5v7Z6ThM7apzI8N9Yrx-Hk7e_aAuMtzPvQSG-7mdPwEAAP__W54e6Q">