<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/88908>88908</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPIR-V] Bit width of input/result types in OpSConvert/OpUConvert must not be the same
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          VyacheslavLevytskyy
      </td>
    </tr>
</table>

<pre>
    Bit width of input/result types in OpSConvert/OpUConvert must not be the same. However, at the moment SPIR-V Backend would produce something like

```
     %4 = OpTypeInt 64 0
     %14 = OpConstant %4 123
     %21 = OpUConvert %4 %14
 OpCopyMemorySized %19 %16 %21 Aligned 4
```

when translating

```
call void @llvm.memcpy.p0.p2.i64(ptr align 4 %dest, ptr addrspace(2) align 4 @__const.test.arr, i64 123, i1 false)
```

for the spirv32 target.
</pre>
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