<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/88851>88851</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Is there any generic cpu model support for RVV?Or how to add a cpu model for RISCV?
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dinyy
      </td>
    </tr>
</table>

<pre>
    While I‘m tryring OpenCL(PoCL) on RISC-V,it call llvm to generate it's kernel. I want to use -march=rv64gcv, but it occurs that I need -mcpu when I use opt. I need a cpu model which support RVV.
Now I change the code in `llvm-project/llvm/lib/Target/RISCV/RISCVProcessors.td` that :
![image](https://github.com/llvm/llvm-project/assets/107465691/ee44f36c-11d4-41e2-9c0c-4a53ab46801c)
but I don't find other place to change,I saw that  [page](https://discourse.llvm.org/t/custom-risc-v-processor-can-be-selected-via-mcpu-in-llc-but-not-in-clang/5849),but code has been changed so much.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUk0-PpDYQxT9NcSkZgfnTcOCw07NISFF2tYkmZ2NXgxNjI9tMq799ZHon2T3kkJNlyti_V--VCEEvlmiA5gWa10wccXV-UNo-Htns1GP4Y9WGcILPHLoC-m7D6B9e2wW_7GSvvwDvvrq09Ogsfpt-u7I3-DzCyxW6q44ohTFozPuG0eFClryIhDoCvwT8i7wlk-OEd2FjOnEEQrYJL1eoXv17Wy_yHfgV5yOijuikPHzAuIqIE1oihWyT-4H3lSxO5-9uj_lHUWAqbk6Rwfuq5Yrh2HfnI357e8uheIXi06_ujhPKVdiFMK6E0ilCbRHaIoGz3bs_SUbgY9qmRc_Ax9-FXyh9TaLfPtav3kkKwfmQRwVt8WSF6tPzMeAlNC96EwtB8wq8W2PcQyrzEfi46Lgecy7d9sNrPzOIECgG4GNZXOq2afsS-EhU17eqlawsVc3qkjjrZSFZLZpKzHXbFaUE3j8ZUi8nVM4Cv0S8aavQxZU87kZISi48mwH8OmEQ96cEhOZl_w9spYN0hw-UJ9jc-QX4mGDlEaLbmNdBsvck4tkbJoVlM7FAhmQkxd61OH1k2jJjJJuPyKyLaSuNsOm6pqv7JIFfE__p0SoCzkT2O6_C4HA75JpnaqhUX_Uio6G8lBVv6rLus3VQZdvxsppF2_D2VlFVViWn5tbOXUedUpkeeMHroi7b4tI0dZ8LUTWF4A0v-ra9lReoC9qENv8ozXQIBw1d1zVlZsRMJpzTxLmlO55F4DwNlx9OK-djCVAXRocY_r0l6mhomFK2yRMK-3hOi5Y_RPgjvDfnU4C_z1k_fvG4untyTqifQ3-ePPNZjdnhzfC_83YqSHk7Ff4dAAD__3-nVqk">