<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/87028>87028</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] Implement more tricks for materializing 64-bit integer immediates
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          efriedma-quic
      </td>
    </tr>
</table>

<pre>
    Currently, AArch64ExpandImm.cpp (AArch64_IMM::expandMOVImm) supports the following patterns for materializing 64-bit immediates:

- 64-bit MOVZ/MOVN followed by 1 or 2 or 3 MOVK
- 64-bit ORR followed by by 1 or 2 MOVK
- Two 64-bit ORRs.
- 64-bit ORR followed by AND
- 64-bit ORR followed by EOR

The following possible two-instruction patterns are not implemented:

- 32-bit MOVN followed by MOVK
- 32-bit ORR followed by MOVK
- 32-bit MOVN followed by ORR
- 32-bit MOVN followed by EOR
- Any MOV followed by ADD/SUB (shifted immediate)
- 32-bit ORR+64-bit ORR
- 32-bit ORR+64-bit EOR
- Any MOV followed by EXTR (rotate)
- Any MOV followed by SBFM/UBFM
- Any MOV followed by BFM (inserting in same register)
- Any MOV followed by MUL/MLA (squaring the immediate)
- Any MOV followed by AND/ORR/EOR with shift (both input registers equal)

The following possible three-instruction patterns are not implemented:

- Two ORR+MOVK
- Three ORR
- MOV/MOVK for low half followed by BFM/shifted ORR for repetition in high half.  (Prefer shifted ORR because it's faster on some chips.)

More notes and a bit of WIP implementation work at https://reviews.llvm.org/D78981 .  (I'm writing this up mostly so I don't lose track of the work I did there.)
</pre>
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