<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/87015>87015</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [InstCombine] Unable to reach fixed point in 1 iteration when new folds are unblocked by knownbits.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          goldsteinn
      </td>
    </tr>
</table>

<pre>
    Take the following examples:
```
define i8 @src(i8 %x, i8 %y, i8 %z) {
  %cmp = icmp eq i8 %x, %y
  %conv16 = zext i1 %cmp to i16
  %conv8 = zext i1 %cmp to i8
  %r = add i8 %conv8, %z
  %cmp_assume = icmp eq i16 %conv16, 0
  call void @llvm.assume(i1 %cmp_assume)
  ret i8 %r
}

```

When run with `opt -passes=instcombine` we run into:
```
LLVM ERROR: Instruction Combining did not reach a fixpoint after 1 iterations
```

https://godbolt.org/z/6Exn4r8jc

The issue is because we try to transform the `%r = add i8 %conv8, %z`
before we get to the `%cmp_assume = icmp eq i16 %conv16, 0`.

But we end up transform `%cmp_assume = icmp eq i16 %conv16, 0`
-> `%cmp_assume = icmp eq i1 %cmp, false` which, with the `assume`,
we are able to use to prove `%cmp` is `false` and thus `%conv8` is `0`
and then on iteration two simplifying the `%r = add i8 %conv8, %z`.

This particular cases is pretty easy to solve by supporting `(zext/sext op)`
in the AssumptionCache, but you could really generate any amount of
these issues by having a fold create a pattern we recognize in
`computeKnownBitsFromCmp` and a having a prior node that
we will only fold w/ certain known bits.

I think the fix is that when we add an `assume`, we need to
also add all instructions in its `AssumptionCache`.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUVV1v4zYQ_DX0yyKGRMWy_eCHJD4Dh15RILi2jwVFrSxeKFIlV_7Iry-WkmMn6PWuQODQ8s5wtDNcqhjN3iFuxOJRLLYzNVDrw2bvbR0JjXOzytfnzVf1gkAtQuOt9Ufj9oAn1fUWoygeRLYV2YMos-kvfa2xMQ7BrEDcZzFoIVe8louTkE8wLs_X5auQaxDLxxEM_Eh3PYhiC4YX-DfcwBP2ptK7Q16m4lc8EZj8gicPJi8_lK6-V7m6KQypSNX1tG8CTnu_vlf5l4px6PC9WNZzUcaw7ILRylo4eFNzY6w9dPMRzg3K3zMKub6gAtIkJEztXm6nxb91f_z8s0UHYXBwNNSCKDPfE9z1Kkb2bWtcJO27yjgUZQZHTLXGkf-eqV--_PErfHp-_u1ZFA_w2UUKgybjHTwlHg5GbWpwniCg0i0oaMyp98YRqIYwQA6GMCgGxf-Q3hL1KVtyJ-Ru7-vKW5r7sBdy9yrkrvx0cvdh9U3fgr62CCbGgT-hQq2GiPxaFM7sLwXlYuNDl6LMG_7I5oumChsfEtUeKVG9Efy8_2U2vxX7OBAToqth6G-0_X_ake9OFJ9-BJ7ixcBG2Tja3hrd8pMUkunFpvwx29NIf0RQAUFVFrkB3Fny0Ad_uOkE85nI39_olauB2iFeilJ_38qu8sc6dODdNSFARw_RdL01zZnD9fPGzd8Hw0ToVSCjB6sCaBUxsoQ-INEZUMWUkOjtAaE6Qxz63gfiLdN2K54WQu4iDw3f88G8CDcuqXrgjvUs-knpFllJNRCc_QDaD7bm82DtGfbo-OUQlDuD6vzgCHwzUlGLcUpwZBWtOrACxWO3Bh0w4aBXRBhcOrCo_d6ZVwTj3k6T9l0_EP7i_NE9Goq74Lun0Rzusrry9sH4AM7XPN0VvTl9NNaCd_Y87nwUcgcaAynj4IVpoTIU37X4M1Br3Mt4S5gTN5cp4ciecnjqGpT7mC3-xSHWQH6KgY1-rLUWzHXARDCcixSaj60us_ms3hT1ulirGW7yZZ6X5aIoylm7WS4lopKy0fn6Hot1Vsi8Xhd6uZCFVsVyZjYyk_dZIVdSFouinOe4WGb6Ps-a9UrJ5VLcZ9gpY-dpVvuwnyWDNqtlli9mVlVoY7o-pXR4HN0TUvJtGjaMuauGfeRZbyLFKwsZsune5TH6NI3hxRZ-d5czNk7QxpywhnGEGnc7P8fe8qbsUkznc3CV9foFa85Psio5NRuC3XyYqYbaoZpr3wm5Y1XTv7s--G-oOe1jEoXcpXf9JwAA__91m4M6">