<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/86620>86620</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISC-V] Vector -flto -O2 miscompile
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          patrick-rivos
      </td>
    </tr>
</table>

<pre>
    Testcase:
```c
unsigned a, b;
signed char d = 0xBF;
long c[12];
int main() {
  c[9] = 0xFFFFF1FFF;
 for (int e = 0; e < 12; e += d - 0xFFFFFFBC) {
    a = c[e];
    b = ({ b > (unsigned short)~c[e] ? b : (unsigned short)~c[e]; });
  }
 __builtin_printf("%X\n", a);
}
```

Commands:
```bash
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/clang -march=rv64gcv -flto -O2 -fuse-ld=lld red.c -o red.out -fwrapv
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/qemu-riscv64 red.out
1FFF
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/clang red.c -o red.out -fwrapv
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/qemu-riscv64 red.out
FFFF1FFF
```

Reduced LLVM IR:
```llvm ir
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

@d = global i8 -65
@c = global [12 x i64] zeroinitializer
@b = global i32 0
@.str = constant [4 x i8] c"%X\0A\00"

define i32 @main() #0 {
entry:
  store i64 68719419391, ptr getelementptr inbounds ([12 x i64], ptr @c, i64 0, i64 9), align 8
  %0 = load i8, ptr @d, align 1
  %conv12 = sext i8 %0 to i32
  %b.promoted = load i32, ptr @b, align 4
  br label %for.body

for.cond.cleanup:                                 ; preds = %for.body
  store i32 %.conv4, ptr @b, align 4
  %call = tail call i32 (ptr, ...) @printf(ptr @.str, i32 %conv)
  ret i32 0

for.body: ; preds = %for.body, %entry
  %e.020 = phi i32 [ 0, %entry ], [ %add, %for.body ]
  %.conv41819 = phi i32 [ %b.promoted, %entry ], [ %.conv4, %for.body ]
  %idxprom = sext i32 %e.020 to i64
  %arrayidx = getelementptr [12 x i64], ptr @c, i64 0, i64 %idxprom
  %1 = load i64, ptr %arrayidx, align 8
  %conv = trunc i64 %1 to i32
  %conv3 = and i32 %conv, 1
  %conv4 = xor i32 %conv3, 65535
 %.conv4 = tail call i32 @llvm.umax.i32(i32 %.conv41819, i32 %conv4)
 %sub = add i32 %e.020, 68
  %add = add i32 %sub, %conv12
  %cmp = icmp slt i32 %add, 12
  br i1 %cmp, label %for.body, label %for.cond.cleanup

; uselistorder directives
  uselistorder i32 %.conv4, { 1, 0 }
}

declare i32 @printf(ptr, ...)

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.umax.i32(i32, i32) #1

attributes #0 = { "target-features"="+64bit,+v" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0}

!0 = !{i32 1, !"target-abi", !"lp64d"}
```

Commands:
```bash
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/clang -march=rv64gcv -O2 reduced.ll -o red.out -fwrapv
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/qemu-riscv64 red.out
FFFF1FFF

> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/clang -march=rv64gcv -O2 -flto -fuse-ld=lld reduced.ll -o red.out -fwrapv
> /scratch/tc-testing/tc-mar-25/build-rv64gcv/bin/qemu-riscv64 red.out
1FFF
```

Found via fuzzer.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMWEmv27oV_jX0hpAgUYPlhRceKuABr3hAXhF0F1AkbbOhSJWkfH2z6G8vDiVLsp0BBVLkXQQOh8PvzB9pU-fkWQuxRcUeFccV7f3F2G1HvZXsc2Tl1bhVY_j79h_CeUadQNkOJUeU7FCZDP_YMO91gOKYInLADcr2w_q4yi7UYo5RdsTJbV9P28roM2ao2KcEFcdpWWqPWyo1IhUiG4zW4zoOshtUHEeoGv7Sup4R8clYjEgFEGKQQtk-DA84JeOY7GGH4-iOUe8PT5owpuE4aBRL42CrCVtg3nofJn-DyRQEdzHWI7L5z_0wRlkd5HbflwPz0PqIyGahDhaG4adPTS-Vl_pTZ6X2pxAfgkjxT1QcdBgeIAPz6enslLBxGj4Ppm2p5u41rQ11l3Ep-FY7ZqlnF0RqzyIvnJf6PExaaiNSIFKDbTyy1zI_syvMIYE1U1SfMUixC8qO4zaOTsobHP1BcHTqnYgUR9lRKY6t4DHDkQkD03scnd4s7a4_x5p_i7aPrHTsWuZ3DQNyqKKf6PGv8mPqiG-n_YPgPRMc__77x7_j3z68Zl-pa4ulHVY9tWfhMaeeKvoOngy1T0TUomwnog5luzIPH5GcBimpULZLSRXpjAxrf6ZDvS5hvZWdEnfI0aOo15-1edORkrq_RWfdT8fGzzwZ2OSsTEMVlhWOymLaY8u9wC74hsG04oi_CGukll5SJb8IO51pHvAygpNpK3beDlxgtPNUe8DMAbICRDb3YLKDj-TJWi5OUosAivJkSWwkS2bOEdrb9ykZGDtvrACzcVmt002ebrJNCh3eeYvPwgslWqE9zKRuTK-5C5T04O9dHqICY4BL7oMNUAVQhpJnjauJcEiRBH-VoRycnDH4LJ4uxJnR15SEM07cPOQjgHgDXi8Em7izpjVe8IWCjCw0NLOG_H6wsVjRRihAOBkbw520DDCsMaN5zJSguoeCxD_6A6rtrICYhdp7Ap7CD0kjBcBf8x-YCYGgSgVAT6XCYTYgVJ23cCSO45D5PJkofESEKguJGTSCQkjPiG2Ff6jKye9gMtwr3_SHHGA6VNdsqYgTMmS5u8hBabEfSuMujcf6gQ1ECsr5uHuHDgIz5BCktEo3L7gPqf-OjjnO31Yj-Q2QFtU2RGzwCEquXKaEWkvfJb8N_f3QNv9Dq8x6F9DpoojLuTpmnV9vLvBxKBLba3aHT1-7BQSzIEk1fyyMw0v_5UHwZuxSMAPJsiiykRznGH-tSvPA_HHf0lscurJ6KH_I7FOF5nOJIlK4fmBRyvlDUoIRywiAwJOg65sx7QOZLL1ruyAtYeDUlPCxIGfZxmKZjidg55U0nhcfWGN5wWR73DuhJLAAFxZzaQXz8ircXdnD9gtNwMMwkHUyv9_mwXgtMEXtdC8s-WBmimej6l4zL43GO-8tPNywNpDAhrLPWJuTFQJr4941w9r0-k1qjl0nWK-op40S-E0qZYXvrcataI19R6TSRotJ15NZX6mIsQbGGyxdmki9t7LpvXDj5QZctIbWJsOFH50E9b0VDu7I7Biuzn2ZN9IjckBkf0WEzBF7hEsnuJ_nM35KCiJp8Lg1vFciPil6vjNqCjc1SZPXE8lCAsKWDpWczl7TRo7P82FZdWXOYeUv-z7_g8C7Et6JsVK__h37__Z1_D7y8l3k1wXgB4_4Gh58-CopPvVfvggbr_g245tsQ1dim67TNCfJuipWl23DyCYnRcoSmlWFKBuaNGtBaFEVaVFu1iu5JQnJk4yUCck2eRGLRDTVhqQirxhZ0zXKE9FSqeLQGsaeV9K5XmyrsiTJKhCqCz8iEKLFGw6bUNzFcWW3cCZq-rMDMpHOuxnFS6_Crw8ffvvzEH2Ex_RHwbyxi6-HrXTMtJ1UYtVbtb1434V-IDUi9Vn6S9_EzLSI1AA7_hd11vxLMI9IHYxxiNTB2P8GAAD__5icyDk">