<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/85882>85882</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] SVE reports cannot select SRAD_MERGE_OP1 when facing srem vxi16 of -1
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            llvm:codegen,
            crash
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          DataCorrupted
      </td>
    </tr>
</table>

<pre>
    ## Reproduction

https://godbolt.org/z/TzvYj99fo

## Scope

This only happens when `sve` is included, with `srem` a constant vector of -1. This happens for upstream and LLVM 15-17.

## Cause

A direct cause is in `AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE`, `Log2_64(SplatVal)` created a potential division by zero(log(1) == 0). Similar for `AArch64TargetLowering::LowerDIV`. 

https://github.com/llvm/llvm-project/blob/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L25956-L25959

However, this bug won't be triggered on vector of 1s or scalar 1 or -1 for the following reason:

In `DAGCombiner::visitSDIVLike`, any divide by vector of 1s or scalar 1 or -1 is already lowered. But a vector of -1s failed to get lowered because `isConstantOrConstantVector(Inexact)` is `false`. `Inexact` comes from `vxi32 splat 16 - vxi16 splat 0`. The weird effect is the bitwidth of element is 16, but the APInt extracted from the elements have bitwidth of 32. With clause `Const->getAPIntValue().getBitWidth() != BitWidth`, `Inexact` is not considered a Constant Vector. Why was this clause there when you [commit it](https://reviews.llvm.org/D25374)?

https://github.com/llvm/llvm-project/blob/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L4825-L4832

## Fixes

- An immediate fix would be to add a guard at `AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE` to avoid any 1 or -1s.
- Fixing `isConstantOrConstantVector` should also be possible, but I need some help on that.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzEVlGPmzgQ_jXOyygITCDwkIfsstmLlKpVs0p1T5XBA7g1NrJNsumvP9lJtlmp6t1JJ91LAjYz_uab7xtg1opOIa5I9kCyasYm12uzqphjj9qYaXTIZ7Xm5xWhKaEpfMbRaD41TmhF4orE68tv79xoSbomdEPoptO81tJF2nSEbn4Qunn5cfzzW1m2-j7omnPf6BHv1196YUEreYaejSMqC6ceFZA8tkckeQzCglCNnDhyQh_hJFwfdg0OfptBo5V1TDk4YuO0Ad3CPIkgJL7lbLWBabTOIBuAKQ673eEDJNk8WUa_QPnIJvsO5Rq4MNg4aPzOBZNHsV6bps8XL8x06Hb6hEaozlOTrsPdRrwi36HqXH8I6LbKVeIoOL7o_eGJ5LGvieTxTnf0a74gtNiPkrkDk4SWvr7GIHPIgcGoHSonmAQujsIKraA-ww80mtBC6o7QIiG0BJJWJK0gJrSMYC8GIZkJBPwDvNX2QPI4gt-0W7h-qqNGD4RupDze_uaj0d-wcYRuaqlrQje8ZpQtMyybJbZF0mKxWC4XNcsQMcN8iXHCizhhd3mEj7uAI3RzBfvzartHeQMdNeNIaLqjWZnl8_BX3qP-Q5_wiMbT67wS6qmDk1aELh3UCM6IrkODHLS6E05iQRuwDfOcJf56ngTuXI_Qain1SagODDKrlefk7sRtUES1fn7UQy0UmguvvlVuX20PO_Edrw1n6hyayNG38G-OFxaYNMj4GaQvHnkED5MD9k7wFlomJHJwGjp0t0ehxotkSR4L-3i1ykdzu7qoktBiq_CV-faVV9ORPG6ZtHjRQx7fHvCa1ANaaI0e_MbxVaQUrJctJDnM4fgqkvy6EIfwlx7hhMJwwLb1NhI2MFoLdxLc9b4ElDigCltJ7kmqJxceWn_aKgf46gxrvBPCuX7jGuFdfnyfK6URfPGDopG34kPBc5I-dehCxgOTExJaeJt06B6E--LDLytAaOJN9Lb6ZtQ7GoQFpV2YP4IHshnceIULsRF86c9wYvYiwisc16PBy5w76wlI9tDoYRAOhCNZRWjx3nIGjwJPNvIuuY7ZimbpcuGblW7-T68-ao7PqAjd7FFieFNU62cP8KcNbk5dFDSb7xZFSn8xcf2gtPfrc1grEMOAXDCH0IpXOOlJ8mBeDYx7truJGQ7M_TejOOQ9asGDP6_2s9ENz0a8eu__3kh5DLYPOJm02oMdtbWilniT9BYUIgerB4Qe5egHkOuZi2Z8lfIyLdkMV8kyiYtyUcbLWb9KGaOU1cgYzeua-24sOG2TZlEmZZHymVjRmC7ilMZxnGbxMuJxjXFZJj6iKNucLGIcmJBvEpoJaydcFVlR0JlkNUobPgsorVnzHRUn6fpt_FJCHwmlofHputEcO9_y63JjmO39XVbNzCrIq546SxaxFNb9VO3MCSfDx8ctcVbB_vAEBkdtnIWGKW8nG4QE-8_r6uuHp8_PT18_fkouZmlZ4zvgX_3XIRNG32wycvWvlR8YsIRuAgl_BQAA__8gUuQo">