<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/85903>85903</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SelectionDAG] Add new ISD Node for vector saturating truncation
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            backend:RISC-V,
            backend:X86,
            llvm:SelectionDAG
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          sun-jacobi
      </td>
    </tr>
</table>

<pre>
    Based on the #73424. There were several patches and issues on the vector saturating truncation operation on different platform.

For instance, #68466 for x86, #75145 for RISC-V vector extension. I think it is better for us to do a target-independent combine for this operation, which could expressed as a sequence of LLVM IR like: 

```
define void @trunc_sat_i8i16(ptr %x, ptr %y) {
  %1 = load <8 x i16>, ptr %x, align 16
  %2 = tail call <8 x i16> @llvm.smax.v8i16(<8 x i16> %1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
  %3 = tail call <8 x i16> @llvm.smin.v8i16(<8 x i16> %2, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
  %4 = trunc <8 x i16> %3 to <8 x i8>
  store <8 x i8> %4, ptr %y, align 8
  ret void
}
```

Especially, I think this combine could be done at the SelectionDAG, like the other saturating operation such as `ISD::SADDSAT`. This could remove complex TableGen pattern matching for this operation. 



</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJysVU1v2zgQ_TX0ZWCDoj4sH3RQorow0N1DHRR7KyhyZLGhSS1JOe6_X5C2N3G2XfRQIGDoGT3OG87MI_deHQxiQ8oHUnYLPofRusbPZvmNC9urRW_l9-aBe5RgDYQRgbB8nResWMHTiA7hJS4eT-i4hokHMaIHbiQo72f0N9gJRbAOPA-z40GZAwQ3G8GDsgbshO66MyDVMKBDE2DSPAzWHVeEdoS2l3VrHSjjAzcCCXuMfKq6qCoYrINzXV1t6zIrymT7vNs_Lr_cCOA5oPHKmhXsIIzKPIMKoDz0GAK6hJg9BAvSAofA3QHDUhmJExoZWQl77JXB9GUYlX9lH0O_jEqMIOysJeB5cujj3XEPHDz-PaMRCHaAT5--_AG7z6DVM5K8hbcZkope_9JPiUMMd7JKAilouravnoevqlZZRVg9BQeElecY_rr_TtgGyPrhcgJEUwYk70BbLoHkjzWcIaLzD29Q6QSu1cFAVr2BsgQNXGkQXOt7fOSk9em48kd-Xp2unN59wsos1eXemj-qrIJlxuro_O37mNvmTRr5L6ahzM_TYD9NI2PrW_Tfs31Pv7jQj-V_zyDmFuy_1pT6FeiDdXjnSWfd98qt6vUN5TCkhrs25Lr7YWde1g9-QqG41umg21ClybiNymUcegRpDQIPSRH2qFHEsenajxEZRyE5bBjxTile5cHPYozDRCq623ckb0ne7tuu27dPpKJRklLUGM3h0Z5i6OOk8QxPvNf4EU2UqIDOwDFKVTz9v3O8uh_HtC5kk8tNvuELbLJ1RjeszOpyMTa0Hxgb6iFjVSElK7igRU4FpQIzUdR0oRpGWUFzRmlNiyJf1UVZFoMY-jov6vWmJAXFI1d6lfrPusMiSWdTlxuaLzTvUfuk0Iz1XDyjkSRv29aJsSoIix1557no3Q8cf0VxvFpjqHh3dzVg8Q1wTfQt-_ng40goH_wrsaCCTq_FHbDsoJUSDL7Abt_Bn1Ze1PH_NH8xO92MIUw-VpFtCdseVBjnfiXskbBtInj5t5yc_YYiELa9vCmEbdPd_BMAAP__nVL4uQ">