<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/85823>85823</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [ValueTracking] Missed optimization: Infer known bits from `a & mask == 0`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          XChy
      </td>
    </tr>
</table>

<pre>
    Alive2 proof: https://alive2.llvm.org/ce/z/L3E65p

### Motivating example 
The automatically reduced IR is:
```llvm
define i1 @src(i32 %conv) {
entry:
  %and = and i32 %conv, 1
  %cmp = icmp eq i32 %and, 0
 br i1 %cmp, label %then, label %else

then:
  ret i1 0

else:
  call void @dummy()
  %and1 = and i32 %conv, 3
 %cmp1 = icmp eq i32 %and1, 0
  ret i1 %cmp1
}
```
can be folded to:
```llvm
define i1 @tgt(i32 %conv) {
entry:
  %and = and i32 %conv, 1
  %cmp = icmp eq i32 %and, 0
  br i1 %cmp, label %then, label %else

then:
  ret i1 0

else:
  call void @dummy()
 ret i1 0
}
```
Note: The dominating condition in real-world IR is `a & mask1 == 0 || a & mask2 == 0`.

### Real-world motivation

This snippet of IR is derived from [qemu/hw/sd/sd.c](https://github.com/qemu/qemu/blob/ddc27d2ad9361a81c2b3800d14143bf420dae172/hw/sd/sd.c#L917) (after O3 pipeline).
The example above is a reduced version. If you're interested in the original suboptimal IR and optimal IR, see also:https://godbolt.org/z/f6qxcocrE

**Let me know if you can confirm that it's an optimization opportunity, thanks.**
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMVd1u7CYQfhr2ZpQVhvXfhS-S7LEUKaeVjqKqt9iM1zQYHMCbs3n6CtvJ7qZN1btWQsbAN8P8fYPwXh0MYkXSO5LuN2IKvXXV7_f9adNYeaputToig9FZ2xF-C30Ioyf8lrCasFrMp1utj8PWugNhdYuE1W-E1Y_8W5aOhO4JvV2_jC8DvtugjiIocwD8KYZRIyyQpx5BTMEOIqhWaH0Ch3JqUcLDD1DzvYuqjC4j3rxsSeyUQVAJkB31riWsUJwBYWlrzZGwEkh-t0DRBHf60AURI4wEwvcQ5yuxe0guYO0wzjAVf_DlHSqMjEi6Ihs3mzHD474WDeq4Dj2aqw3UHi9DNAPOhjkMURO9hMwiZ0iMEhytktFtOQ3DibCCsPLat-Qr5_iKW4xNvnAuufTu3apVZLUt33_KzLJshYEGobNaooRg_3UGwyH8hxn8P6Xwk4YvAv2LDVEnRAZJOyiz0Ku1RqqgrAFlwKHQN6_W6ZVOQDIqgLAMBuGf5-TH0FAg-T3J7-F8xj7OSEa3f0_qH2ftw8pvay6hT73y4I0aRwxgu9UGiU4dUULn7AAkvXvBYSKs7l8Jq72cP9uWpHvCiuvec1Chn5ptawfC6lVqnRptG8JqKVuWSyZkybNEFEnLGl5QKpNdsuNNt2NUCkxy9tfrGH8sk3wuOVaILqCDXzmMakStDBJWbs_96r2DicYeMXokPprWEZ1X1mzhoYOTnQjLHYIyAR36gDLmJPQI1qmDMkKDnxo7BjUIHYMTK_m8jEXnEUFoH1n0KRZWNlaHtQfH9ttlLz9b27pv18mK4xEDDAjPxr6Cmg2DSNPWmk65AUIvAqhAWO5BmMUC9TZnE-w4Whcmo8Ip2hN6YZ79dlG7kRWXJS_FBqskT2iR5VmWbfpKFJQlecpzVmDalZkoWZrkku12De8KLjaqYpTtKE_KJKcJzbZUFLTjCfJd1_CyKMmO4iCU_nhoNsr7CasiLRjfzFT07y-YqyLoppkOnuyoVj74s1hQQc9v3W9CT_jkRPuszIGke_iuvEd55W2k04Pp0M2hMtCo4NcyveTNJTU2k9PVP5Tp3OyW6WZ09g9sA2H17IwnrJ79-TMAAP__1pgxlw">