<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/85658>85658</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[DirectX]DXIL] Design and implement TableGen DXIL Op record specification using Attr
</td>
</tr>
<tr>
<th>Labels</th>
<td>
backend:DirectX
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
bharadwajy
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
bharadwajy
</td>
</tr>
</table>
<pre>
Current implementation of TableGen DXIL Op record specification in `DXIL.td` leverages type specification of LLVM TableGen class `Intrinsic` while using an overriding mechanism when more precise types need be specified.
Design and implement an alternative specification mechanism that has the potential to be more readable yet has sufficiently rich representation for the `DXILEmitter` backend to generate information for the DXIL Lowering pass. This is Option 4 as outlined in the [DXIL Design document](https://github.com/bharadwajy/llvm-project/blob/dxil_td/design-doc/llvm/docs/DirectX/DXILOpTableGenDesign.rst).
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyMU8GO6zYM_Br5QjzDkWMnOfiQVzfFAin28lDsraAlOtZWlgyJTpq_L2RnN-2iKHoJFJma4cyQGKO5OKJGVN-FlN2AAfUN3-9CSlG1Gc48-NA877PO63sjilYUx5_mEMgxmHGyNJJjZOMd-B5-YGfpF3LQvr2c4XWCQMoHDXEiZXqj1kLjQNRFKslZi7oAS1cKeKEIfJ_oS7Xv4Xz-7dcntrIYY0J4cRyMi0YljNtgLMEcjbsAOvBXCsHo9G8kNaAzcYTbQA5GHwimQMpEWvgiOCIN3Scx6RxWpetvS8ksQKefkhMHWqbgkM31a89PSh6QYcAIPBBMnsmxQQvsE9_SSiDUSRrcaa2Mc98bZcixvUMwaoBAU6D4aXTvwwL3MPHn0TBTSCZ0qP4gpxP8hRwFZALjeh_Gf75c4jn7G4Vk0IQx5vBjMBFMhNdpKd0CRvAzW-NIp8gWxur78vThiPZqTmaIqhVyPzBPUZRHIU9Cni6Gh7nLlR-FPP19vk7WXsdvU_DvpDh9s74T8qT_NPZ31um0gH_TXj2K051XUchTawIpfkunt5fz6_QxE2s_eYgs5CFfU8t0U-pDecCMms1uU-x2h-2hyIYGUWLX6QJ1XWrc4gHr4rCtse-LEitZZ6aRhdwW5Wa_qcuN3OXFTteV2ktdbfReVTuxLWhEY_PUXe7DJTMxztTsq7raZxY7svFjs9ZERHn87H1ZsNAsNnTzJYptYU3k-ERjw3ZZzY83VZv0iqqFf53F_7d2624cmUM2B9v8R1wP078EtWhMKSwy_woAAP__s4NygA">