<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/84937>84937</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Missed optimization: indicate knownbits from dominating condition `cmp(trunc(a))`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          XChy
      </td>
    </tr>
</table>

<pre>
    Alive2 proof: https://alive2.llvm.org/ce/z/oiLdtM

### Motivating example 

```llvm
define i32 @src(i64 %addr, i32 %0) {
entry:
  %trunc = trunc i32 %0 to i16
  %cmp = icmp eq i16 %trunc, 1
  br i1 %cmp, label %sw.bb, label %fail

sw.bb:
  %and = and i32 %0, 65535
 ret i32 %and

fail:
  call void @dummy()
  ret i32 0
}
```
can be folded to:
```llvm
define i32 @tgt(i64 %addr, i32 %0) {
entry:
  %trunc = trunc i32 %0 to i16
  %cmp = icmp eq i16 %trunc, 1
  br i1 %cmp, label %sw.bb, label %fail

sw.bb:
  ret i32 1

fail:
  call void @dummy()
  ret i32 0
}
```
NOTE: real-world case is a switch, see also: https://alive2.llvm.org/ce/z/NdBYVJ

### Real-world motivation

This snippet of IR is derived from [qemu/hw/core/loader.c@load_aout](https://github.com/qemu/qemu/blob/8f3f329f5e0117bd1a23a79ab751f8a7d3471e4b/hw/core/loader.c#L247C13-L247C20) (after O3 pipeline).
The example above is a reduced version. If you're interested in the original suboptimal IR and optimal IR, see also:https://godbolt.org/z/Woa6n1rW1

**Let me know if you can confirm that it's an optimization opportunity, thanks.**
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzcVVuv4yYQ_jXkZXQiA3ZsP-ThXBppq71Iq1W3farAjJPpYvACTpr99RV2cs7Jqhf1oS-VkAHPMLdvPlAx0t4hbln1wKqnlZrSwYftz4-H80p7c97eWzqigDF43zN5D4eUxsjkPRM7JnZqlq6tPQ5rH_ZM7DpkYveNiZ2ntya9Y8UTK-4vXyGXAe98oqNK5PaAv6thtAg3iptiGdnu8stgTw6BpABWFjF0TDS0KYGJShkTmHhcZKIqmGiB1Q_LOXQpnHO48w6yQgqT64DJJ1hW13OQPBDfvNLshnHWo7zAr1n6bCB75FddHYD45UQWWKXR5n08rbW--dMrsq9zXTRuAlTOzG7z_JLUI2yqSlYXvYDpKlPOvDY4O3ix1ylr4ejJ5LqZaRjOTDRMtFf51VBxsVE_fYfBsu2UA43Qe2vQQPLPHv4Rq7RP_1esrrXj_33933_49EOmX0Bl704-WAOdiggUQUE8UeoOOfSICMpG_6-Y-t48_PLTj3_O1I8v_oYLab17rfrpQBGio3HEBL6HNx9zTAYDHdFAH_wArHr4isPExO5wyn59yJ6tVwbDumNlkZe_Kj8lVj0x0dwGvqd0mPS68wMTu4udy6St10zsml72UrR9hQXntTZcCanqVum64n2jaiPLmmOp_yoAId-Ksn7k8m6exdKVolF9wgAfJIw0oiWHTLTra9b4fHMp7Y8XIAKaqUMDRwyRvFvDmx7OfmKiDgjkEgaMCQ2Qg3RA8IH25JSFOGk_JhqUzfXLvH_Zfgfrd8XxRnubLohmMD97tXE8fOa3eObxFhMMCF-cPwHNgUGmdeddT2GAdFAJKDFRR1BuiYC-zYCDH0cf0uQonXM86aDcl7hezK7MVppWtmqFW17zQlQtL8rVYVu2fFN3upJa17LXpeSFaeu6kgVvOG_UiraiEGUhueBV1Qi5LorWtLqWhgvBa1WxssBBkX1u2xXFOOG2KVtZr2aexvnlEsLhCWYhEyI_ZGGbz9zpaR9zh1FM8cVKomRx-45iRHOTaOYNOUOdSkuhnKYUlzY2fiC3PFqdd4bmwrBNMd8jzeWiaVTmtmjZplhNwW7_ppfnC3OZ7sbgf8MuMbGbc4i5q3OOfwQAAP__A7Y5MQ">