<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/84799>84799</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV][MCA] Failure to use SEW from instrument on vmslt.vi
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          preames
      </td>
    </tr>
</table>

<pre>
    In the test case below, we appear to be failing to apply the SEW from the vsetvli to the vmslt.vi.  Note that we do apply it to the vmslt.vx. 

I haven't fully tracked this down, but I suspect the fact that vmslt.vi is a assembler pseudo instruction and is actually encoded as a vmsle.vi is a relevant factor.  In particular, if I use vmsle.vi directly in the assembly, the problem goes away.

```
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s

vsetvli zero, zero, e16, mf4, tu, mu
vmslt.vx v4, v8, x10
vmslt.vi v4, v8, 10
vsetvli zero, zero, e16, mf2, tu, mu
vmslt.vx v4, v8, x10
vmslt.vi v4, v8, 2
vsetvli zero, zero, e16, m1, tu, mu
vmslt.vx v4, v8, x10
vmslt.vi v4, v8, 12

# CHECK: Iterations:        1
# CHECK-NEXT: Instructions:      9
# CHECK-NEXT: Total Cycles:      68
# CHECK-NEXT: Total uOps:        9

# CHECK: Dispatch Width:    2
# CHECK-NEXT: uOps Per Cycle:    0.13
# CHECK-NEXT: IPC:               0.13
# CHECK-NEXT: Block RThroughput: 58.0

# CHECK:      Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK:      [1]    [2]    [3]    [4]    [5] [6]    Instructions:
# CHECK-NEXT:  1      3     1.00                  U vsetvli     zero, zero, e16, mf4, tu, mu
# CHECK-NEXT:  1      4     2.00 vmslt.vx       v4, v8, a0
# CHECK-NEXT:  1      19 17.00                       vmsle.vi   v4, v8, 9
# CHECK-NEXT:  1      3 1.00                  U     vsetvli     zero, zero, e16, mf2, tu, mu
# CHECK-NEXT:  1      4     2.00                        vmslt.vx        v4, v8, a0
# CHECK-NEXT:  1      19    17.00                       vmsle.vi        v4, v8, 1
# CHECK-NEXT:  1      3     1.00                  U vsetvli     zero, zero, e16, m1, tu, mu
# CHECK-NEXT:  1      5     3.00 vmslt.vx       v4, v8, a0
# CHECK-NEXT:  1      19    17.00 vmsle.vi      v4, v8, 11

# CHECK:      Resources:
# CHECK-NEXT: [0]   - SiFive7FDiv
# CHECK-NEXT: [1]   - SiFive7IDiv
# CHECK-NEXT: [2]   - SiFive7PipeA
# CHECK-NEXT: [3]   - SiFive7PipeB
# CHECK-NEXT: [4]   - SiFive7VA
# CHECK-NEXT: [5]   - SiFive7VCQ
# CHECK-NEXT: [6]   - SiFive7VL
# CHECK-NEXT: [7]   - SiFive7VS

# CHECK:      Resource pressure per iteration:
# CHECK-NEXT: [0]    [1] [2]    [3]    [4]    [5]    [6]    [7]
# CHECK-NEXT:  -      -     3.00 -     58.00  6.00    -      -

# CHECK:      Resource pressure by instruction:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6] [7]    Instructions:
# CHECK-NEXT:  -      -     1.00    -      -      - -      -     vsetvli        zero, zero, e16, mf4, tu, mu
# CHECK-NEXT:  - -      -      -     2.00   1.00    -      -     vmslt.vx       v4, v8, a0
# CHECK-NEXT:  -      -      -      -     17.00  1.00    -      - vmsle.vi      v4, v8, 9
# CHECK-NEXT:  -      -     1.00    -      -      - -      -     vsetvli        zero, zero, e16, mf2, tu, mu
# CHECK-NEXT:  - -      -      -     2.00   1.00    -      -     vmslt.vx       v4, v8, a0
# CHECK-NEXT:  -      -      -      -     17.00  1.00    -      - vmsle.vi      v4, v8, 1
# CHECK-NEXT:  -      -     1.00    -      -      - -      -     vsetvli        zero, zero, e16, m1, tu, mu
# CHECK-NEXT:  - -      -      -     3.00   1.00    -      -     vmslt.vx       v4, v8, a0
# CHECK-NEXT:  -      -      -      -     17.00  1.00    -      - vmsle.vi      v4, v8, 11

```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzUWN9z2roS_mvEyw6MLWF-PPCQQJgyt017k7S9bx1ZXoNubMsjyaScv_6MhMGEYgLnpDPnaDK2FH_ab_eTtIvNjZHLAnFColsSzTq8siulJ6VGnqPpxCrZTBYF2BWCRWNBcIMQY6ZeCJ3CCwIvS-QarIIYIeUyk8XSjXhZZhs_7_HuO6Ra5X6wNmjXmXQIP8xNZntr2QO4VxbBrrh1VpOdAWmPoD97QIIZCW621wWs-BoLQocW0ipzlJqLZ0zArqSBRL0UztG4srAAU5kShfXmUu473O59AGmAAzcG8zhDDaXBKlEgC2N1JaxUBfAi8ShhK-64sBAqwQS4m-ns4N6OxgzXvLCeSOkewKKAkmsrRZVx7ZySKSygMtjMTKRGYV3YW8lrZzYO7calVnGGOSwVGuAvfNM71IIMgvpvO6QM7j8_3RF2AzfGoHYhGK8XxIgF8MqqJRaoucUE4g1UVmaG0HlVJtzij1zwH27Rf4gVimfTKzeN4Yev985ulq3zbi44dHOrZZkhYTMtjVgP-tDNRVkRNjMylWvs_qSjALrSOjrnCGGzEAibAqGRATKcwlxmOHVU_l-Hke12zR-oldNid8dw4G552vcKVX5Q1XPq_QJr_3A9ctefYfDqqXz1dP_wLTr6LnT0MrbwfWKjr7YKZTD9cDf9j1vExcGa3EDdwiNg9_7uf08e3ZyHBj9uQz8pyzOYbkSGDXowOg-vPpeHroxbPZ9JU3IrVvBdJnZVT6Ftxp1Z-IJ6606NDnohaw31y_TAjbqdm3CbKfEMD08rrarlqqys-2c06gWtEfh2ICksilQRdgzdM5DoNiTRzHcp80K1I2mN_MgtFmJzBslq5KHr7eh-jf7ENx8VT84gowb5aJXGM9BBDf3AzaNM8C5NUVgDhI6-Etq-BXyrVam7tOmypttvus6rHeWR_uaM9hBu2dj2gPSCAH5pX3cVjgTja7JVO1vfX6lj2x17EowPjzYP3rIRjiEcnvTXt139ObLbeqgbIdpE8FbfFuJEHr1IiDNx_FV93PV6iVqz5HvtlRPJv50s2lL-3a2yl6It6PD8aXxAoyot8NxZItFtsD19XXiUc7nG4Xwm12-kvUP44jycHsG_yBLPecNO4G_fyIGH-G_njEfH4Ol_38iEr9Afz4CHx-DHyxYHSo3GVBqhRA37n2UXLdl-OS5OttvuoOk6t1u3YnfrarfZztuuq6QBwKA-TTvYtQHHm8Mf9ddFfE2FOQi6WaiLi80rEcKjkHe3V-N3qzzdX3igybwnXbk-3Zxi2AW7zcO_EF1dpn6LhJfVrH-XhO1l7HdIeFlNO60g-6cqGJ58E-8kE5aM2Zh3cBIOwyAcjvrDfmc1SWhA0zgY9Xk0iONIJKMgEHEUsTgVQ8bTjpzQgPYDFobhkPUZ641jRmkwTClPxJizMekHmHOZ9dw7eE_pZUcaU-Fk1B-Ox52Mx5gZ_1WH0piLZywSwm4eFo_T7jdCXQLr6Il_fY-rpSH9IJPGmsaYlTbzX4XclG8uW0e3n6Y3LonNucxcHrXKf73Yf9_ZJtUcCwuq2H9W6VQ6m6ys9a90hM4JnS-lXVVxT6ic0LljrG_dUqv_o7CEzn0shtC5D-fPAAAA___al88n">