<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/84815>84815</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RegCoalescer] Bad machine code: Live segment doesn't end at a valid instruction
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:optimizations,
            crash-on-valid
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          JonPsson1
      </td>
    </tr>
</table>

<pre>
    ```
cat tc_crash3_aftercreduce.ll
define i64 @f(ptr %b) {
  %2 = load i136, ptr %b
  %3 = lshr i136 %2, 32
  br label %4

4: ; preds = %1
  %5 = trunc i136 %3 to i64
 ret i64 %5
}

llc -mtriple=s390x-linux-gnu -mcpu=zEC12 -O3 -disable-machine-dce -verify-machineinstrs tc_crash3_aftercreduce.ll

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    f
- basic block: %bb.0 (0x2aa03c3f3b8) [0B;256B)
- liverange:   [176r,224d:0) 0@176r
- v. register: %1
- segment:     [176r,224d:0)

```

It seems that the coalescer is messing up the dead-flag(s), and the resulting live-range is broken:

```
 dead %1:gr64bit = INSERT_SUBREG killed %10:gr64bit(tied-def 0), killed %11:grx32bit, %subreg.subreg_l32

=>  # *** IR Dump After Two-Address instruction pass (twoaddressinstruction) ***:

  %1:gr64bit = COPY killed %10:gr64bit
  dead %1.subreg_l32:gr64bit = COPY killed %11:grx32bit
 
=>  # *** IR Dump After Live Interval Analysis (liveintervals) ***:

208B      %1:gr64bit = COPY %10:gr64bit
224B      dead %1.subreg_l32:gr64bit = COPY %11:grx32bit

=> # *** IR Dump After Register Coalescer (register-coalescer) ***:

176B      %1:gr64bit = SRLG %4:gr64bit, $noreg, 24
240B      dead %0:gr64bit = LGHI 0

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    f
- basic block: %bb.0  (0x2aa03c4e5c8) [0B;256B)
- liverange:   [176r,224d:0) 0@176r
- v. register: %1
```

@DianQK @aeubanks ..?


</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMVk-P27YT_TT0ZSCDGkqyfPDBf3bz21-DJt2kh54WlDiS2aUlg6ScTT59QUr2eoPNNoeiKGBQxszjI9_oDUXpnG47ohXLNyzfzeTg971d_b_vPjrXd-ms6tXXFSv49OM7xte19ODrh9pKtxcPsvFka0tqqGluzAhR1OiOQBcZsIw3DMujt8AwrxgugS02IwxCCIGJHZheKtCpKBhu4QJ-RokR5fY2ouLEABV4BlUWjKzIhFQ2BscxY2INTGzgaEm5yMMwT6_I8xj0dujqC7sA3wcBE8ySH-Vgnk_ki931KsbUkBy81UdDTOycWPKnxOhueEraboDkUB8HJnbfbrYpQvJBQKK0k5Wh5CDrve4oUTVBciKrm6_nmO6ct-7vqj2NOP1gIxVMBFD3ioL-9_pE4Kg9UOdB9eQ6hgsP1CmQHiScpNEK4npD7XXfwYVvpE-gGbqYCXQA0JzjlXS6hsr09WOsNOZVNefAsORPKCUXtWhEVcY3n2_4hokN5sWG4fLMYPSJrOxaGqlZvkkXhWW4RcwUE2se5nKW8RieJp3mYKnVzpOdlk3PqUnntNHX-V6U7qXBx_HOgyM6OPD7YPh9qKU05GqyoB0cyDndtTAcY06RVEljZMuwdIEetyA7FXOW3GB8AAehSVQaKCrbP1Io5xt7icSjOLFubZFV2ke33v366eb-88On3zf3N-_gURtDI44_AxmWXpNKFDXAp01dIUfKJ4ERug0xN1SW2vn4eDDn7ppGsWPiJnSMeHYH3N3DbjgcYR2sCZ-_9MlaKUvOvXDTUToXLOG_9HJMX2WjNS52e1kPeE389sPHP36keZp1qdu1mLdZXtRjpPl54bHB7jpP9iQNrDtpvjodJYeXrqeEe0sq8nIDo2N_IPlVrYjZNO1nNb8u9oXWt6TeT20H20tDMCzPzZhc2uQtremi-LHWT_fv343H-JWVgz-zrrfUhv84HcyY8e_E8-_I3r_73x3w__JJeX1UZpTX_95R-erBxzK-07L77Zfw7ZY0VLJ7dDCfM3F7DZuplVBLsZQzWqWLlKdlwdPFbL8qmrxYYFGgXDSlqhpRVWlODYlMliku1UyvkGPGRZqmy7DReVNIRMI0k7LmWb5gGaeD1GZuzOkw7207084NtCqzMs1n8Svv4pUFMSCYWPdHrw_6mwxVdwzD1YAhxo9m0ndJfGchnO9mdhXmJNXQOpZxo513z-t47U28Dd1Te3E3y3f_jFNmgzWrvfdHF7oBbxnettrvh2pe9weGt1HM-EiOtv-Tas_wNmp3DG-j_L8CAAD__zaivMc">