<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/81192>81192</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[RISCV] Compiler abend when compiling for rv64 with Zb due to instructions producing i32
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
nemanjai
</td>
</tr>
</table>
<pre>
This test case:
```
define void @func(i32 %0) #0 {
entry:
%mul = mul i32 %0, 6
%conv = sext i32 %mul to i64
tail call void null(i64 0, i64 %conv, ptr null, i32 0)
ret void
}
attributes #0 = { "target-features"="+64bit,+m,+zba" }
```
Causes a segfault in the compiler when using `-pre-RA-sched=list-ilp` as the register pressure calculation tries to get the register class ID for the `i32` produced by `SH1ADD` and used by `SLLIW`.
Invocation:
```
llc -mcpu=generic-rv64 -march=riscv64 -pre-RA-sched=list-ilp
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJx0U01vpDgQ_TXmUqJlyjTdfeCQNGptpDnNrHalvRlTgEfGIH90NvvrV3aTyeQQCeGvV89Vz6-k93qyRC07PrNjV8gY5tW1lhZpf0pd9Ovw1v45aw-BfAAlPTHxxHjH-BNr-P7l5UCjtgT3VQ_Aaj5GqxietUBgeOQML8BQcGCn5weebHBvv8ggoZZogIkO0vgReIXmN4xa7T2DPP0b3lEpIKygm_odGaQ2oKQxj4RsNCZl09SQGdNkJ0vLLbgdcs2UKd13Jkchc-xFn7p9kv8yBKf7GMjv1YkuVQgMMUg3UShHkiE68gyRiS798bmpex0YXhk-L4_hv14yRPhg_6ztVUZPHiR4mkYZTQBtIcwEal02bcjB60wWotd2AtbwcnNUfn8qvZppYKIz2odSm401HKTPkY4m7QM52Bx5Hx0ltVQ0MujVQnCafJJ0ovAZroz0Hl46GFeXT1jDtcDEvLl1iIoG6N_S7o8_qqeuy1faAaL_OPj27eVv1vDD70q-2Puq8uVfGcwYBeWitshEN5Elp1Xp7k0N5SKdmpnonPYqb3xV_mfaYmjFcBEXWVBbnfipxnPNRTG3VV-dcLiMo6hOSEdsuORSNBd55Ej1uSp0ixxrjvyMVc25OJAYj7KXnC7NiRT2rOa0SG0OxtyXw-qmQnsfqT1X1QULI3syPvccoqVXyIfJG8eucG2KKfs4eVbzlLr_YAk6mNys319-XP9ixw6u7w6QPdnh4YOHK5IX0iNljV51mOGfHoZIuVOsDy6qJLff3y3BtcAiOtPOIWw-vQPeGN4mHebYH9S6MLylVPah3Nz6k1RgeMsFeIa3XOD_AQAA__9ReEyH">