<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/80554>80554</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            mips1 target generates invalid instruction
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          cmccord-dev
      </td>
    </tr>
</table>

<pre>
    The issue seems to stem from insertDivByZeroTrap, which is inserted after division instructions.  The MIPS I ISA didn't have the trap instructions.  They are correctly marked as being added in MIPS II in the InstrInfo.td but manually instantiated here. 

I think the correct sequence for MIPS 1 would look something like
bnez $divisor, label 
nop //delay slot
break 7
label:

https://github.com/llvm/llvm-project/blob/2fa6b546356394bb60dfc8090d4594c6c4c0cbd8/llvm/lib/Target/Mips/MipsISelLowering.cpp#L1277
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUUs1unDwUfRqzuQoyxjDDgkXyRSMhJdInJavu_HMBd4xNbTOj6dNXZqZqFt10w4WLzo-Pj4jRTA6xJ80LaV4LsaXZh14tSvmgnzReCun1rf-cEUyMG0JEXCIkDzHhAmPwCxgXMaRXc3m5fcPgP4NYCfsPrrNRM5j4-I8axJgwgDYXE413eZ_CppLxLpYAWeN9-P8DBhg-nkEb7Qg7JJjFBSHNCCmI9S-gG4iAoHwIqJK9wSLCOYtFkGjcBEJr1GDcg3zIr5luyEyDG32ZNMgtwSLcJqy97RrCJSOy6RkDlkDoK6HP9-cAaTbuvJM8ZCHijw2dQhh9uAtVcPWb1WC9P0P0C2bQBNac8U4jHf4Ewviehw85Misk2oeW8ysQdiLspNGKG0Tr0wMYUJzhcP_YIaR-_mpwTmmNebfDJ5PmTZbKL4SdrL38Hk9r8N9RJcJO0npJ2ImNopUNb-umrTsuZUv1qI60o5o3HVet4ooqqY9feEzGfYowYeZ5N2t8jOED7Zu_YjBuKtW6Ela_VexwKHRf667uRIF9daBtd6RtcyzmHruuqwTvODYVG7uxqhmreUNpxxmVvCtMzyjjlNG6OlSHui1b3rStqhsqVdV0nSCc4iKMLbO50oep2CvbH2nT8GIPKu5FZ8zh9d5nwljufej3ROQ2RcKpNTHFPyzJJIv9YtZYQdqPChM6DCJhLvdFWKO_9rLYgu3_-Q52Ozm93e6vAAAA__-PtSz_">