<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/80099>80099</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Sources with different EEW must use different registers
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            preames,
            rofirrim,
            lukel97,
            kito-cheng,
            BeMg
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          topperc
      </td>
    </tr>
</table>

<pre>
    At some point this text was added to the vector specification

> A vector register cannot be used to provide source operands with more than one EEW for a single instruction. A
mask register source is considered to have EEW=1 for this constraint. An encoding that would result in the
same vector register being read with two or more different EEWs, including when the vector register appears at
different positions within two or more vector register groups, is reserved.

The RISC-V backend does not emit any instructions for bitcasts that change element size. This can cause us to use the same register with different EEWs. See an example here https://godbolt.org/z/WTGKfxo3f

Filing this based on a message on the mailing list here https://lists.riscv.org/g/tech-vector-ext/message/919
</pre>
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