<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/79918>79918</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Suboptimal register allocation which prevents the use of compressed instructions
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          petrhosek
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/TjYxcYaTe shows the output from Clang and GCC for the following example:
```c
int in1;
int in2;
int in3;
int in4;
int in5;
int in6;
int in7;
int in8;
int in9;
int in10;

int out1;
int out2;
int out3;
int out4;
int out5;
int out6;
int out7;
int out8;
int out9;
int out10;


void testit() {
    int x1 = in1+1;
    int x2 = in2+1;
    int x3 = in3+1;
    int x4 = in4+1;
    int x5 = in5+1;
    int x6 = in6+1;
    int x7 = in7+1;
    int x8 = in8+1;
    int x9 = in9+1;
    int x10 = in10+1;


    out1 = x1;
    out2 = x2;
    out3 = x3;
 out4 = x4;
    out5 = x5;
    out6 = x6;
    out7 = x7;
    out8 = x8;
    out9 = x9;
    out10 = x10;
}
```
When targeting Arm, LLVM reorders the operations only needing two registers, but when targeting RISC-V, it doesn't do that and ends up using too many registers which prevents the use of compressed instructions pessimizing the binary size. GCC appears to have the same issue.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUVU1vpDgQ_TXmUkoLjMFw4JB01KuVZi87o1nN0UDReMbYyDZpkl-_4mPSiZfLSi2a91657HoUhXBOXjViRbInkj1HYvK9sdWI3vbG4a-oNu1r1Xs_OpI-Enoh9HI1bW2UPxl7JfTyRujl288fc_NDfENwvbk58D2Cmfw4eeisGeCshL6C0C38cT5DZ-wa0RmlzE3qK-AshlHhskP8TOJHksfbr9mw1B6kTkj69BHTAKcBZgHOApwHmAe4CHAZ4CR-J-60mfznc5rJ05BIQ4KFRBYSeUjwkChCogyJ_xx4u74Y2YJH56UntCC0BML3MACAZfGcAEmf12dAn-71vct0l-mxnO5yeiyzXWbHcrbL2bGc73J-LPNd5sdyscvFsVzucnksJ_FvX-JPAR-vS_Bi_ho5f06yNMfG05DfPJvvrbL2yUayMHizaM5CfvNmzkN-M2XmIb-5MRchv9kwlyG_1z9_7Cz-HLzEG_ynRw1e2Cv65ZV_tAOhZ_jy5ftfYNHYFu0-N0a0wkujHRitXkEjtssCfzNg8SqdR-uWpfXk4fY56d9_fj0_fF9E6aE16DShfLkD3wu_DiDUrYNphMmtSY2BQejXe2a49bLpYbT4gtpvR5ocgumgMcNo0TlsQWrn7dRsxxzROTnItzVhj1BLLewrOPmGp3XgiXFEsZRnoBcvuAY5MSBI5yY8RW2VtmVaigirhMd5xhnLWdRXiIy3edk1CUtFhyzr4qTo0qJseZ4WNIlkRWPK4iSN45hyxk5l2TKe8qTjaZ4LzgmLcRBSnZR6GZaBHa1bVrwskyJSokbl1tFPaS2aX6hbkj7-dpEuHwRbLUsf6unqCIuVdN7dk3npFVZfp9qMXg5CvdsIQinTrI_x_xsaTVaFnxzp-6k-NWYg9LJsv_89jNb8xMYTelkLc4Re1tr-DQAA__9yufsA">