<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/78262>78262</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[RISCV] 2006-07-03-schedulers.ll failed when LLVM_ENABLE_EXPENSIVE_CHECKS is ON
</td>
</tr>
<tr>
<th>Labels</th>
<td>
bug,
backend:RISC-V
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
wangpc-pp
</td>
</tr>
</table>
<pre>
The assertions after ISel:
```
# After Instruction Selection
# Machine code for function testissue: IsSSA, TracksLiveness
Function Live Ins: $x10 in %2, $x11 in %3, $x12 in %4
bb.0 (%ir-block.0):
successors: %bb.1(0x80000000); %bb.1(100.00%)
liveins: $x10, $x11, $x12
%4:gpr = COPY $x12
%3:gpr = COPY $x11
%2:gpr = COPY $x10
%5:gpr = COPY %2:gpr
%6:gpr = COPY %3:gpr
%7:gpr = COPY %4:gpr
bb.1.bb1:
; predecessors: %bb.0, %bb.1
successors: %bb.1(0x7c000000), %bb.2(0x04000000); %bb.1(96.88%), %bb.2(3.12%)
%8:gpr = ADDI $x0, 7
%9:gpr = LUI 259686
%10:gpr = ADDIW killed %9:gpr, 1638
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = COPY %7:gpr
$x11 = COPY %10:gpr
PseudoCALL target-flags(riscv-call) &__mulsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%11:gpr = COPY $x10
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
%12:gpr = LUI 258048
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = COPY %6:gpr
$x11 = COPY %12:gpr
PseudoCALL target-flags(riscv-call) &__mulsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%13:gpr = COPY $x10
$x10 = COPY %13:gpr
$x11 = COPY %11:gpr
PseudoCALL target-flags(riscv-call) &__addsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%14:gpr = COPY $x10
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
%15:gpr = LUI 259072
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = COPY %7:gpr
$x11 = COPY %15:gpr
PseudoCALL target-flags(riscv-call) &__mulsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%16:gpr = COPY $x10
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = COPY %6:gpr
$x11 = COPY %7:gpr
PseudoCALL target-flags(riscv-call) &__mulsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%17:gpr = COPY $x10
$x10 = COPY %17:gpr
$x11 = COPY %16:gpr
PseudoCALL target-flags(riscv-call) &__addsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%18:gpr = COPY $x10
$x10 = COPY %18:gpr
$x11 = COPY %14:gpr
PseudoCALL target-flags(riscv-call) &__addsf3, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%19:gpr = COPY $x10
%0:gpr = COPY %19:gpr
%20:gpr = SLLIW %5:gpr, 3
%21:gpr = ADDW %5:gpr, killed %20:gpr
%1:gpr = ADDIW killed %21:gpr, 7
BLT %1:gpr, killed %8:gpr, %bb.1
PseudoBR %bb.2
bb.2.bb2:
; predecessors: %bb.1
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
%22:gpr = COPY $x0
$x10 = COPY %22:gpr
$x11 = COPY %1:gpr
$x12 = COPY %0:gpr
PseudoCALL target-flags(riscv-call) @printf, <regmask $vlenb $x0 $x1 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x8_x9 $x18_x19 $x20_x21 $x22_x23 $x24_x25 $x26_x27>, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x2, implicit-def $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
%23:gpr = COPY $x10
$x10 = COPY %22:gpr
PseudoRET implicit $x10
# End machine code for function testissue.
*** Bad machine code: FrameSetup is after another FrameSetup ***
- function: testissue
- basic block: %bb.1 bb1 (0xaa8daa8)
- instruction: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
*** Bad machine code: FrameDestroy is not after a FrameSetup ***
- function: testissue
- basic block: %bb.1 bb1 (0xaa8daa8)
- instruction: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
*** Bad machine code: FrameSetup is after another FrameSetup ***
- function: testissue
- basic block: %bb.1 bb1 (0xaa8daa8)
- instruction: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
*** Bad machine code: FrameSetup is after another FrameSetup ***
- function: testissue
- basic block: %bb.1 bb1 (0xaa8daa8)
- instruction: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
*** Bad machine code: FrameDestroy is not after a FrameSetup ***
- function: testissue
- basic block: %bb.1 bb1 (0xaa8daa8)
- instruction: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
*** Bad machine code: FrameDestroy is not after a FrameSetup ***
- function: testissue
- basic block: %bb.1 bb1 (0xaa8daa8)
- instruction: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
LLVM ERROR: Found 6 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0. Program arguments: build/bin/llc llvm/test/CodeGen/Generic/2006-07-03-schedulers.ll -pre-RA-sched=fast -debug -print-after-all
1. Running pass 'Function Pass Manager' on module 'llvm/test/CodeGen/Generic/2006-07-03-schedulers.ll'.
2. Running pass 'Verify generated machine code' on function '@testissue'
```
I don't see this for AArch64 and X86, so this may be caused by RISCV-specific codes.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzsWltzo7gS_jXySxeUJO4PfiC-7PFZz0zKzmb2PLkEyFgnGFwSZCf__pSELzh4krlkzm6qnEqB3fq61XR_jURjppTIS86HyLtB3njAmnpTyeFfrMx3qbXbDZIqexrebTgwpbisRVUqYOuaS5gteYGcGOExwjHy8f6__UodiFtUqWrZpFoRlrzg5tMJ9IGlG1FySKuMw7qSsG7KFlxzVQulGo6cGGZquYwRHcGdZOmDmotHXnKlWjvTg4oW6wm1BqLuF4JBlICoR7WqkZC9xDlK6F7i7p0yxySxMSAaIuoJaSVFlT7YGNHoeL0AqklTrlQl99N5SWITREP8JcTtn8HfdIYIxrYWe3pkb6YQj1x0XT65enLxADZuOnG-k4CcMYw-3f6nj3AuIkgHQS8icAfh9REHrQ7Kv4ByeqjgAsrtoo4hJ3aSkBOlnBvYSZ7xXpj3MWrD-mo6gvSUjqMeNUPY_UqmIt8Ow32iznQcm9BuAvfTI-qFncuMx-OZCarxNOgEI-qg5n_MgHqRH_odAMHP7HyGB1EUPOtoa6PEd8KDWjz-9yiez5d38ej38afPH8FMaw5iuytEKmor42vIOMuMW7Q7tJccXTB1001W8Dylpo66iIPTB8it4k1WaZ-gZjLntbUuWK4QDaVQ6aOVsqJANAJE_dVq2xRq3dajM5I83zL1oCd5LHiZtFFs5zTH0ByjVtJ-Ie032sJoi6O0PTntyW1PXnvy21PQWlwdza1OtlYnQ6uTldXJxOoLDZAz-XqQSS_IBPdFpGegl6Cj9FSi3Yz_cftz-fYIefl-8Lb08gjt1UCI3QOZfzGX_de5TK9cfsdcvrz64RcoQXpLVp8T5Cc4wbLsyonv48TbUuLylulX3N70bF5_hccB_ecs1d719vaOb28Xtty_aqn-21ficzJfifquiHrhqe-1dfgbbl7-dR1-x5wIv58T4euccK-ceL97s-jVVhS-0D46qHV7Wl3ccj6ffe70sbQPThdMzpssz7GnjgvFvZnICw2ag-Gzts_N_K6jd24_PAmfNbRaHt8sjs2n814ZtZOEfkOvjJz1qd76WZ5ebCW-VNG010bsV_QFBD1D_Gi7ycU7Kcp6fS34o-hytf9f1wX6_c_sz1jUEmAxueuFoEN-RB2YlBlsX3_lYJ_r7f_hhp1r6yqbSrblS143OxCHNyOsrOoNl92xo5HWpnWcVNsA6Lzt2I8nTIkUzJuHTjFDkmiihPgLY2HGWHhsRFsgTm9atMbbVfo3h2HMVS2rJx2IsqoPwfjnhOFnmHrlwjUM15K4BuF5EObz-w8wWSw-LczlVk2ZgX--xnApK6n2a8rtfBIvJ6CaZCtqYJA0OUi-q2QNdQWbut7pzRuiU0Snuag3TWKn1RbRaVE8Hk7WTlb_5WmN6NQERSE6BVZmIMq0aDIO9YZDKpnaQMLSh1qy9LCkLWuWPkDWbHfHvSO2EY5uZZVLtgUm82bLy9rsIJNGFBmi00SUZuYU9k7odCA6HVUZ_43rsd94yaVIEZ1SjH0LBxZ2LJVueNYUXCq7KMDaSW4t4laKnPGaqRqsjOsAWGZbZhliWHqzZhwj2rFFU5aizGHHlAJEg-PL_lst-MBKlnOJaABVCdtKT6dRP-4nosE-VPTS9PdcivUT5NoOq_kzwrduHPcTiAbIxSfu0uDyjyXMcQZZVSIa1KC4zqBQZnMSxzLd-K5J75-hr2moqnZ4y54g4ZCyRvEMkidYzJaje0vteCrWIjUuKXuQDZ0sciI24EMSYM_FXhgFg80Qs8zhJCPumvrc80KaRWHiewHOOKZh5A7EkGLqYkJ8QjziBHYUMOKvfZdESZTyNUYu5lsmCluH265kPjDXOQxC6tNBwRJeKPPDEkqTJkdUF5H-zNIHXmbIibXD1r0e8MYDOTTcTppcIRcXQtXqZLgWdWF-pGKuEXlj-CrR1kzoh6u_NrwEXZ2rycf4Zj5ZTf68nXxczu4nq9G_JqPfl_p29OnjoJHF8MfLzlzq_wIAAP__E3TORg">