<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/77805>77805</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Incorrect code generated for float llvm.maximum/minimum intrinsics
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86,
            llvm:codegen,
            llvm:SelectionDAG
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          danilaml
      </td>
    </tr>
</table>

<pre>
    I believe [this change](https://github.com/llvm/llvm-project/commit/7bff37783f72ed99e4cdd0fd7dad1bf1f119f793) introduced a bug preventing correct handing of signed zeroes in certain cases.

This check
```cpp
  if (Op->getOpcode() == ISD::BUILD_VECTOR ||
      Op->getOpcode() == ISD::SPLAT_VECTOR) {
 for (const SDValue &OpVal : Op->op_values()) {
      if (OpVal.isUndef())
        return false;
      if (auto *C = dyn_cast<ConstantFPSDNode>(OpVal))
        if (C->isZero())
 return false;
    }
    return true;
  }
```

Returns `true` by default, marking most BUILD/SPLAT vectors as known non-zeroes preventing the negative zero check generation.

See this example: https://godbolt.org/z/Yh5oE916v
```llvm
target triple = "x86_64-unknown-linux-gnu"

declare float @llvm.maximum.f32(float, float)
declare <8 x float> @llvm.maximum.v8f32(<8 x float>,<8 x float>)

define <8 x float> @foo(float %a, <8 x float> %vec) #0 {
entry:
  %splatinsert = insertelement <8 x float> poison, float %a, i64 0
  %splat = shufflevector <8 x float> %splatinsert, <8 x float> poison, <8 x i32> zeroinitializer
  %res = call nnan noundef <8 x float> @llvm.maximum.v8f32(<8 x float> %splat, <8 x float> %vec)
  ret <8 x float> %res
}

attributes #0 = { "target-cpu"="haswell" }
```

I believe the check should look something like
```cpp
 if (Op->getOpcode() == ISD::BUILD_VECTOR ||
      Op->getOpcode() == ISD::SPLAT_VECTOR) {
    return llvm::all_of(Op->op_values(), [](const SDValue &OpVal){
      if (auto *C = dyn_cast<ConstantFPSDNode>(OpVal))
        return C->isZero();
 return false;
    });
  }
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMVl9vo7oS_zTOi5WI2CHAQx7S0FxVWt2utrvVvfelMvYAvjU2sk223U9_ZEPStMnu-aPzcBACYw8zv_H8xjPMOdlogA1Kb1BaztjgW2M3gmmpWKdmlRGvmztcgZJwAIzSG99Kh3nLdAMoLRHJW-97h-gWkT0i-0b6dqgW3HSI7JU6HF_z3pr_A_eI7LnpOhkGWVXXNMtyWmcERFHAiguR1CITTCyrelkvl0WdFRSRAkvtrREDB4EZroYG9xYOoL3UDebGWuAet0yL8G1qHL0S-AdYAw5LjTlYz8KbOXALlJQo2Y7Pr6NDwJ-n2XUy3rzvxxmMZY0Rye_7OaK3Dfj7nhsBiOQBGaIloiW-eyjDJtDtzbe7T-XT4-3u6_0XjLJduCc14fpjSh4-f9p-nZTE9exmUlIbG7Bwo53HD-UjUwNgRNb3_SNTGNHtZMH0T4ew5kYL75XE6-jUI1ML6b5pAfVJ9lwOYwt-sBrXTDlA9IoSNniDEdnugiNYvOonzpxHdLcLMJn2-88P5b-Du_T2aPOaoVHbLuCX7n9gzUdAP0WCsvLtY5LydjgXOomcInxOgy_xH4fROon_rRNcvWIBNRuUR2SHO2afA7s64zyOQUZkH-OED8C9sQ4zh5-1-a6xNno-ce-Mp74FrKFhXh4gUnOkHW5Ag2VeGv2OmA8AOGYbvLCuVxBi-yHZjKiM8gtjG0T2PxDZ_7dNzW2xXB8-eBozMU55Zhvw2FvZK4jhQoS85Oun9Wo-6Ah_rqQeXuaNHhAh54gEcMUs4FoZ5jFaRbWLjr3IbugWNSWI5HEt7Nc0KN7_iuguxy_TIr29UHLIRzUf5BDZXcwU76HVUl9VXxtzhIURSVnAdiFG0gPwmCOEJm-JAtrb17DdRwqR1PWKeakdWB93bxyCgg60v1DcG-mMPm3HCYBcr3DyUWvU59qhrhWMlLoG9AzANVfeLE4rkpIwH_gmtfSSKfkD7JltCy5a5kwprDUL9B3CafBXg3VC-cutPiKwcLltI6opvqe0jU_mvZXV4APoGKvA4OwmsHik9pz3kbe0RIS0zH0HpRAhv5P-bzUuZOmYl641gxJYGfOMnenAtyGLlXyGn1aKf1CheDsHY_JHaabUk6lPCC9qxA6PfcBPC0yQulZF_q4CMCG-rACnY_yXFeBc8ErAZ2JDRUELNoPNMktWRbEq8tWs3dTJivGCMkoEX6ZcsLQQ1TpdVTlUNE2XM7khCVkly-Vyma1okixSSJnIeQKk4kTUBK0S6JhUi5ggxjYz6dwAmyzLk3SmWAXKxSaLkIrxZ9AC0e1_8nVgKtkhQqYghVA3oD9OP4ACHipEuf1XWEvLmd3EvqoaGhfyUjrv3ox76RVs7vSxNQpqj3UGRGwixgPpPJ8R2XdSh1Fst6R2krvZYNXmT_d40XkXerzg_28BAAD__66DCv4">