<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/77459>77459</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[x86][codegen] Poor AVX512VBMI codegen when using intrinsics
</td>
</tr>
<tr>
<th>Labels</th>
<td>
clang:codegen
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
gchatelet
</td>
</tr>
</table>
<pre>
The following snippet byte-reverses two `zmm` and returns matching elements into a mask
```
uint64_t big_endian_cmp_mask(__m512i max, __m512i value) {
const auto byte_reverse = [](__m512i value) -> __m512i {
return _mm512_permutexvar_epi8(
_mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, //
8, 9, 10, 11, 12, 13, 14, 15, //
16, 17, 18, 19, 20, 21, 22, 23, //
24, 25, 26, 27, 28, 29, 30, 31, //
32, 33, 34, 35, 36, 37, 38, 39, //
40, 41, 42, 43, 44, 45, 46, 47, //
48, 49, 50, 51, 52, 53, 54, 55, //
56, 57, 58, 59, 60, 61, 62, 63),
value);
};
return _mm512_cmpeq_epi8_mask(byte_reverse(max), byte_reverse(value));
}
```
GCC 13.2 compiles it down to
```
vmovdqa64 .LC0(%rip), %zmm2
vpermb %zmm1, %zmm2, %zmm1
vpermb %zmm0, %zmm2, %zmm0
vpcmpb $0, %zmm1, %zmm0, %k0
kmovq %k0, %rax
ret
```
Whether clang 17.0.1 compiles it down to
```
vpcmpeqb %zmm1, %zmm0, %k0
kmovq %k0, %rax
bswapq %rax
movq %rax, %rcx
shrq $4, %rcx
movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F
andq %rdx, %rcx
andq %rdx, %rax
shlq $4, %rax
orq %rcx, %rax
movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
movq %rax, %rdx
andq %rcx, %rdx
shrq $2, %rax
andq %rcx, %rax
leaq (%rax,%rdx,4), %rax
movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
movq %rax, %rdx
andq %rcx, %rdx
shrq %rax
andq %rcx, %rax
leaq (%rax,%rdx,2), %rax
vzeroupper
retq
```
The issue comes from `InstCombine` transforming
```
%0 = bitcast <8 x i64> %max to <64 x i8>
%1 = shufflevector <64 x i8> %0, <64 x i8> poison, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%2 = bitcast <64 x i8> %1 to <8 x i64>
%3 = bitcast <8 x i64> %value to <64 x i8>
%4 = shufflevector <64 x i8> %3, <64 x i8> poison, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%5 = bitcast <64 x i8> %4 to <8 x i64>
%6 = icmp eq <64 x i8> %1, %4
%7 = bitcast <64 x i1> %6 to i64
ret i64 %7
```
into
```
%0 = bitcast <8 x i64> %max to <64 x i8>
%1 = bitcast <8 x i64> %value to <64 x i8>
%2 = icmp eq <64 x i8> %0, %1
%3 = bitcast <64 x i1> %2 to i64
%4 = call i64 @llvm.bitreverse.i64(i64 %3)
ret i64 %4
```
The `@llvm.bitreverse.i64` operation is then done using GPRs instead of vectors.
Godbolt link : https://godbolt.org/z/5PjzaTr51
llvm-mca latency for the vector version : https://godbolt.org/z/K36K4r16K
llvm-mca latency for the GRP version : https://godbolt.org/z/7qcceYvM8
Is there any way to prevent the transformation and stick to the vector intrinsics ?
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzsmFtv47YSxz8N_UKsId50efBDNmkWiz0FFkXRc86TQUu0zUYSFZF2nHz6A46k8SWumx7sS4F6Ay7N4fx_wxFHoqy9t5vWmAVRn4l6mOld2Lp-sSm3OpjahNnKVa-LX7eGrl1duxfbbqhvbdeZQFevwXzqzd703ngaXhwlafLWNCRNqG4r2puw61tPGx3KbXQ0tWlMGzy1bXBU00b7J5I8kORubNNk_IOvO9uGVC4DXdnN0rSV1e2ybLoluPF8uWwU45Y2-kD4PZ2-7nW9M4QXlGSfBx1KS9f6QPUuOAh6OQZNiXigw8JP9FDgExE_oeyJGh1XRpdNtC070ze7YA573S9NZ3PC8-PU-BnneRMmexIjZrHhsRGxkbFRsUljk8WG8Mf4d6Z2-cnjxAIEB1nQZSDMQJmBNANteq7JgMUAxkCJgRQHKT6ECFJcvAuIgy4HXQ5CHIQ4CHEQEiAk2EdXI4aEAEyAvgB9AfoC9AXoi-KjmhJikBCDBH05ZBz0JehL0JcfzrqEGCTEoEBfgb4CfQX6arik6p2mApgCmAIhBUIpCKUglIJQKgjk8TyYaYsSMW1Kkj0cv1zsz7LpzDPsvKl0TouA8BwqCAK4MCDnBBVJ16p1aL_cx00357R0TWdr46kNtHIvLQ3uqhul-8btq2edSjr_130Si4er3nZjRISrt6bhODkW22ocZacTsMuuzk2uzj0G0ZVNF-fK5FTpZOLQfZo8nhq3fx5HBlOvDyf5v5Gjf29N2JqelrVuN5Rl82TO_kq-OrigV5LwLsjbUa78i-6eLwYnh364q8ZeiUa_7aNxqJtzU-P2euXBypJcsYSrgquMMZUkhZrmVwdKuKC2aeDemxwek7N_k5puq-fR4R3qik2fRFifR3g0uf55EnpnO4lepHkhZJ4zmUlWsERMN77oeRG9uPjcSGJ1eLe28opxyjB_H-MVv6OxNjoac4RiguSxkK4vOGUyL5hMC8ZFqljGE_WHC1YXnx-24B-wUH51ofs307td15l-HOlNeL5RnPGoY73fmViRxtN175p4rvna-nDvmpVtTTzfhF63fu36xrab63VKuEogaysbSu0DJeI-pwdqUxnPFYSrRh9ocHE8ldGQE_HTFDbhioG33-7W69rsTRlcfz4XELDis9HOWe_as3HBYbq4t4LDI-WeQo9jj2EvmXrDIwl6OfYy7KXYU9iT2EOGQoZChkKGRIZEhkSGRIZEhkSGRIZEhkSGRIZAhkCGQIZAhkCGQIZAhkCGQIZABkcGRwZHBkcGRwZHBkcGRwZHBkcGQwZDBkMGQwZDBkMGQwZDBkMGQwYikICA4_XGFGMeMFhUnDrJ-Z7mlxVxvpvZWA_HOjnxFberCc4qt-pJfqSexD_19E89_X3qSd2uJ3mrnlLwtWXTUfN8pRbJ8CyVJy7ZdRwbXdKIi5zjMTh-Bc8bj1zb_uFZ9wc9RP__mwa_naTpVM1u3afOk8QvkoR3plLX9ZAumdT1vpmvbBhfxeZxPs_HXMIr4fsUyz851cSh68ppQl1neh2sa6n1NGxNSyvXGrrztt3QL99_8dS2PhhdUbemw83Tz89e_Fy1cnWgtW2fKBF3dBtC54m4G158N4N57voN4Y9vhD-q77-_6V_7KXVDG6P71JSa1jqYtnyla9fHcEYkjTHHID8C-CbSb7Jn6bc_kf7yy_e_pJs9l6X57_7n_DTwr5C13lDdvtIX_Rovchdz3AaA4HlxSLJuK-qDLZ_ivJP12Tb0tvW29JSIx1m1EFUhCj0zC5YlMk8US5PZdrFWQlV5UsksLUquuSjWnJlsnVUVk0XCZ3bBEy4TlhSMq4IVc61SlnJVVjJTbMVLIhPTaFvPYT-4fjODQ-8iy6QqZrVemdrDb4Kcw2sqEXelq8zGtIRzoh5m_QISutptfNxV1gd_1Ao21PCT4iFPiXog6vPkrB7od-d6evfbfxTjv33--SsdTfQl7rphwx3TMNv19eLiitiw3a3mpWsIf4zI8b9PXe9-N2Ug_BHW4uO1isv5XwAAAP__VxZL1Q">