<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/76769>76769</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            likely miscompile of vector code by AArch64 backend
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            miscompilation,
            NEON
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          regehr
      </td>
    </tr>
</table>

<pre>
    I'm pretty sure this code is getting miscompiled by the AArch64 backend:
```llvm
define i32 @f(ptr %0) {
  %2 = load <4 x i8>, ptr %0, align 8
  %3 = zext <4 x i8> %2 to <4 x i32>
  %4 = add <4 x i32> %3, %3
  %5 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %4)
 ret i32 %5
}

declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
```

llc gives:
```
_f: 
        ldr     s0, [x0]
        ushll.8h        v0, v0, #0
        uaddlv.8h       s0, v0
        fmov    w0, s0
        ret
```
but this is just adding up the values, the other addition that doubles the value of each vector element seems to be getting dropped, the immediate argument to the ushll should be 1, not 0.
</pre>
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