<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/76623>76623</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [InstCombine] Missed optimization: fold `other_cond && (a s> -1) && a s< b` to `other_cond && a u< b` when `b` is a specific constant
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          XChy
      </td>
    </tr>
</table>

<pre>
    Alive2 proof: https://alive2.llvm.org/ce/z/DT9eDZ

### Motivating example:

```llvm
define i1 @src(i32 %a, i1 %other_cond) {
entry: 
  %cmp1 = icmp sgt i32 %a, -1
 %or.cond = select i1 %other_cond, i1 %cmp1, i1 false
  %cmp2 = icmp slt i32 %a, 10086
  %ret = select i1 %or.cond, i1 %cmp2, i1 false
  ret i1 %ret
}
```
can be folded to:
```llvm
define i1 @tgt(i32 %a, i1 %other_cond) {
entry:                                      
  %or.cond = icmp ult i32 %a, 10086
  %ret = select i1 %other_cond, i1 %or.cond, i1 false
  ret i1 %ret
}
```
However, it folds if we replace the logical `and` with a bitwise `and`. I thought that Reassociate should be to blame, but [godbolt](https://godbolt.org/z/fY5vPx951) told me that similar fold for bitwise `and` is handled by InstCombine. Therefore, I tag InstCombine here.

### Real-world motivation

This snippet of IR is derived from [qemu/net/util.c@net_parse_macaddr](https://github.com/qemu/qemu/blob/7425b6277f12e82952cede1f531bfc689bf77fb1/net/util.c) (after O3 pipeline).
The example above is a reduced version. If you're interested in the original suboptimal IR and optimal IR, see also:https://godbolt.org/z/Ea8GGxKba


**Let me know if you can confirm that it's an optimization opportunity, thanks.**
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJycVc2O2zYQfhr6MlhBoizJOviwWcfpog1aBDm0vSxIcWSxoUiVHNnrPH1BSZu1U6Mp1iAskDOcGX7f_IgQ9MEiblnxjhW7lRipc377-0N3Xkmnztt7o4_IYfDOtSy_h45oCCy_Z3zP-F5M0sSYY584f2B83yDj-6-M73efa9z9ydIdS--Xf57PCz460kdB2h4An0U_GIwWL1XLdF7R8nyksNUWQWfA1mnwDeMbnXNgvBCMP0znvHDUoX9qnFWM18Cqd_NdtOTPMfp5C1G16YcMWL4D3fQDhAPBpbm7bFGNRn0SLU7KAQ02dMPbSwTR7LJrhQl47ZFfeDTXHrM03ZQX2h7phsc5lCt3_Ja7eHvW8EgLptXuO3DnbSMsSITWGYUKyL1S8QMS6EBvIuF__S6QuMR_gm58E3Q3yLqG860A_uROeEQ_WaEJxwC6hROCx8GIBoE6BOMOuhEGWJkKq1iZwklTBwKkppMO-CpI4BGoc-OhI6BOEHxCEYJrtCCE0LnRqEgYOZBG9Bj9ypGAFe8OTklniBU7xjfXlbqIliqNBdr-URx_e66LLLJEzijocfYXdK-N8NNToHX-3yGCDtAJqwwqkGd4tIEeXC-1xQQ-d-ixdX4K7BFIHC7lEKXJ7bbwCYW5OzkfQ1k6hLOXqp87HSBYPQxI4Fp4_BQDUej1ERW03vURhb-xHxnfWyTG9yNpkzRsnVqkp0H4gE-9aIRS_iZKmrpRJo3rGd8vdpaPNE4yvq_WvJAlr6o247jhdcEbVJi1RZ7Jtik3tWyrqpXZ9wHESuAb0RJ6-DWHQQ9otEXG6-TlbfjSDEFId8T4NAEe1diggiP6oJ1N4LGFsxsZrzyCtoQeA6ECbacsc14ftBUGwijdQLoXJqIkrILXbSQmIIIwIVb7jxLlvdh8-PD8sxRXrC3cxfULUsydL9adYuKf3QixqTTOttr3c05pYrwKIOwch_46kQtuGJyn0Wo6x6ioE_ZLSGazK7XNVZ3XYoXbrErzuqirNV91W5RcqjormrqQtWxVKkrk6ypPuSxr5GKltzzlecbzNNukdZolVZlzmaeZ2lRp0TaSrVPshTbfJtdKhzDitipLnq-MkGjCNBI5t3iCScg4jxPSb-OdOzkeAlunRgcKr1ZIk5lm6UXGs2IHH3UIqK6eHjvhVGCsTF97EzBeMl5OuQKB5e_jJJpyZzqezh5AxhIkd_uqgPGbzqlDG7XkUrMCwoCNbnUT2QkkLK1Gb7b_UQVT858_d4N3f2ETs3pCJMR6iIj9EwAA__9Runil">