<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/76072>76072</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            ARM hard-float codgen issue when -Oz present
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ltertan
      </td>
    </tr>
</table>

<pre>
    Consider the following code:

```C
volatile float init=0;
volatile float *stage=&init;

float f1 = 0, f2 = 143;

int main()
{
        f1 = *stage * 3.14;
        if (f1 > 1.0F) {
                f2 = 3.14F/f1;
        } else {
                f2 = 0.0F;
        }

        return 0;
}
```

When compiled with the next set of options:
```
-mhard-float --target=arm -mcpu=cortex-r52
```

It will produce valid code, as the `vdiv.f32` is inside the LBB0_1 block (as a result of the `vcmp.f32` logic)
```
 vcmp.f32        s0, s2
        vmrs    APSR_nzcv, fpscr
 ble     .LBB0_2
        b       .LBB0_1
.LBB0_1:
        movw    r0, :lower16:f1
        movt    r0, :upper16:f1
        vldr    s2, [r0]
        vldr    s0, .LCPI0_1
        vdiv.f32        s0, s0, s2
```

When compiled with the below set of options, it fails to restrict the vdiv.f32 and it may end up in a division by zero scenario:
```
-mhard-float --target=arm -mcpu=cortex-r52 -Oz
```

```
        vcvt.f64.f32    d16, s0
        vmul.f64 d16, d16, d17
        vcvt.f32.f64    s0, d16
        vcmp.f32 s0, s4
        vldr    s4, .LCPI0_4
        vdiv.f32        s2, s2, s0
        vstr    s0, [r2]
```

I am able to see this behaviour on all versions between 9 and 18. Have not checked for older than 9.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJysVV2PozYU_TXOy1WQMYSEhzzko1FX2mpX24c-roy5JO4aG9mG7Myvr2wgk6QzK1XqaBRD7rkn1-ccMHdOnjXilqz2ZHVc8N5fjN0qj9ZzvahM_bI9GO1kjRb8BaExSpmr1GcQpkaS7Qg9Ejp_FnT8P4z3g1HcS4XQKMM9SC09yY6UZPt364TtnOdnJNmRsGJE7-_5R1iTAsmOQAk7QMPidZpnT1CpPbRcasI2hJVTZX2DlBPJ_JPhArIkze9oStkAYZuI_A3ShJ4IK-GeJPCMA4TWE2GnJr0nIOsjoHL4QRMNlI_wBzVpadH3VsObYm-QWer7jr8uqEGYtpMKa7hKf4meafzpwaEH04DpvDTavRn3yLNsL9zWy1Ho5dJze8bgGbctLFvR9SQ7CmM9_lzaFfvFKJ88XKVS0FlT9wJh4ErWY2bYAbiLg5GCDrUckiZjpKAgHcgYtVj8vN_T7ylUyogfwQfugINF16u4kblftN3cr8xZije3H8eCGQnTn4sBctMm5m-H1rqw7r7--e27fhVDTFnnhJ1wlcIITOJ8T93VtI7FdCzON7PkM7g1wzWsNg5Csp0yV7RpQbJdk_4L6h-gfdd9AB1UbeP2WISu9paS1fEDTKRLPh--frpNe8NMxjzJ9SDafwlhhcpcn1PIDiA9NFwqB94Ed72VwseG2wBc1wHV8hdAXUPfgdTAoZaDdNJoqF7gFa0BJ1BzK83_k21Yfnn9xS6f0zWrJgafNEU-K1enxSTbU8p6FWBz_bas36PLWMTeTAjoJ9gU7cme_AO78zu7nzHPdrPJ6Pemd_4uPiFi7Bax918GwFvg4cnxBhyG51s6qPDCB2l6C0YDVwoGtMHQUPFXRA1l9D7dJPA7HxC08SAuKH5gDY2xYNR4KnENZbKot1ldZiVf4DZd04xuNkVJF5dtmZdpiaxZlWnO0rRIS17yzSavqrIoGcsXcssoy1LGaFqkaUaTci0yXhScM1GvckFJTrHlUiVKDW1i7Hkhnetxuy7omi0Ur1C5eIAypvEKsUhY0GRht6FnWfVnR3KqpPPujcVLr3C7-_YH3AVTmPqMeiSBa3iWll9eobPoUPtFb9X24n0XX-AsnDhn6S99lQjTEnYK1NOy7Kz5G4Un7BS5HGGnOPA_AQAA__-hXizu">