<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/75543>75543</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [Codegen][RISCV][X86] Emit float instructions with static rounding mode for constrained intrinsics.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          boomshroom
      </td>
    </tr>
</table>

<pre>
    IEEE 754 section 4.1 describes floating point attributes with 

> An attribute is logically associated with a program block to modify its numerical and exception semantics. A user can specify a constant value for an attribute parameter.

LLVM's constrained floating point intrinsics are the only thing in LLVM to provide the constant attribute behavior without constant-folding from the environment manipulation intrinsics. Some modern ISA extensions also allow specifying the rounding mode statically within the instruction, both better matching the desired semantics of the constrained intrinsics and saving instructions setting and restoring the global floating point environment.

However, LLVM does not currently use them without target-specific intrinsics completely detached from the target-independent intrinsics which take the same information. For RISC-V, these intrinsics are paradoxically only available for vector operations, which _don't_ have the option of a static rounding mode in the instructions, but there aren't any intrinsics for scalar operations which _do_ have that option. X86 on the other hand does have intrinsics for both vector and scalar operations, but that seems to be because they're provided by the same extensions.

Currently, constrained intrinsics are lowered to strict opcodes with rounding mode striped completely before reaching the target-specific code generation, preventing the desired behavior.

Source (note that static rounding mode in AVX-512 only supports suppressing exceptions, hence specifying `!"fpexcept.ignore"`): 
```llvm
define float @div(float %x, float %y) {
entry:
  %div = call float @llvm.experimental.constrained.fdiv.f32(float %x, float %y, metadata !"round.downward", metadata !"fpexcept.ignore")
  ret float %div
}

declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
```

Output with llvm 17.0.1

On X86 with AVX-512F:
```asm
div:                                    # @div
        vdivss  xmm0, xmm0, xmm1
        ret
```

On Riscv with F and hard-float ABI:
```asm
div: # @div
        fdiv.s  fa0, fa0, fa1
 ret
```

Expected output

On X86 with AVX-512F:
```asm
div:                                    # @div
 vdivss  xmm0, xmm0, xmm1, {rd-sae}
        ret
```

On RISC-V with F and hard-float ABI:
```asm
div: # @div
        fdiv.s  fa0, fa0, fa1, rdn
 ret
```

Godbolt link: https://godbolt.org/z/7fPoEoxs8
</pre>
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