<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/75276>75276</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
             "unexpected implicit virtual register def" when rematerializing in register coalesced
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:regalloc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    ```
# Run: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing -run-pass=register-coalescer -o - %s

---
name: remat_into_subreg_copy_implicit_subreg_def
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $rdi

    undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0
    %1:gr32 = MOV32r0 implicit-def dead $eflags
 %2:gr64_with_sub_8bit = IMPLICIT_DEF
    undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2.sub_8bit

 bb.1:
    %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags

  bb.2:
    JCC_1 %bb.4, 5, implicit killed undef $eflags

  bb.3:

  bb.4:
    dead %3:gr32 = MOV32rr %1
    dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags
    %1:gr32 = COPY %2.sub_32bit
    JMP_1 %bb.1

...

```

Running this hits:
```

Assertion failed: ((MO.getReg().isPhysical() || (MO.getSubReg() == 0 && MO.getReg() == DstOperand.getReg())) && "unexpected implicit virtual register def"), function reMaterializeTrivialDef, file RegisterCoalescer.cpp, line 1425.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing -run-pass=register-coalescer -o - /Users/matt/src/llvm-project/llvm/test/CodeGen/X86/coalescer-unexpected-implicit-virtual-register.mir
1.      Running pass 'Function Pass Manager' on module '/Users/matt/src/llvm-project/llvm/test/CodeGen/X86/coalescer-unexpected-implicit-virtual-register.mir'.
2.      Running pass 'Register Coalescer' on function '@remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg'
 #0 0x00000001041fd270 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x101fcd270)
 #1 0x00000001041fb7f4 llvm::sys::RunSignalHandlers() (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x101fcb7f4)
 #2 0x00000001041fd8d8 SignalHandler(int) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x101fcd8d8)
 #3 0x0000000186427a24 (/usr/lib/system/libsystem_platform.dylib+0x180467a24)
 #4 0x00000001863f8cc0 (/usr/lib/system/libsystem_pthread.dylib+0x180438cc0)
 #5 0x0000000186308a40 (/usr/lib/system/libsystem_c.dylib+0x180348a40)
 #6 0x0000000186307d30 (/usr/lib/system/libsystem_c.dylib+0x180347d30)
 #7 0x0000000104ef7fa4 (anonymous namespace)::RegisterCoalescer::reMaterializeTrivialDef(llvm::CoalescerPair const&, llvm::MachineInstr*, bool&) (.cold.46) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x102cc7fa4)
 #8 0x0000000103a7f8a0 (anonymous namespace)::RegisterCoalescer::reMaterializeTrivialDef(llvm::CoalescerPair const&, llvm::MachineInstr*, bool&) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x10184f8a0)
 #9 0x0000000103a7c730 (anonymous namespace)::RegisterCoalescer::joinCopy(llvm::MachineInstr*, bool&) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x10184c730)
#10 0x0000000103a7aca8 (anonymous namespace)::RegisterCoalescer::copyCoalesceWorkList(llvm::MutableArrayRef<llvm::MachineInstr*>) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x10184aca8)
#11 0x0000000103a78d40 (anonymous namespace)::RegisterCoalescer::runOnMachineFunction(llvm::MachineFunction&) (/Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc+0x101848d40)


```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMWN9v6joS_mvMi5UocQwJDzxwoeztqlURPbt79wk5ziT41nEi2-kp-9evnB9AKJW61a3OVogm9njm-z7PjBOYMaJQAAs0_Q1N1xPW2EOlF0wbUOUkrbLjAs2C_hOsUbBEJMK7RqFoiaXk2CutFrUEFK3fktl-Rr2ae1Ko5s0rVIO9V9AiP3q8YhIMF6rAnm6UVzNjULTWUAhjQQ_zoLFXYQ8jMjV9uPbb87zuQrESXGgNJbN7oWy1N02qodjzqj7uRVlLwYUdBjPIu3VWM_5idlA8iFdQ4IIvsdUNdNOOqBu5_EPxqpvEOE39AEXL4RZjKV5BqNYJIlRn4hKsM2hUBrmjEfimSfcRSYVF0bLQM7r_KezBAdwnqbAYRWv8-PTPiOgAD_A9tzgDljnvkEtWGERW42nn-xwPkWnY-o_Ipz12ixGZko-R3T9uH-5X9z_267vNDXbkM-xWT9t_dwBvcOg8ONuRhGnqhyPFPxvsj6ddRLS4ticr_D78LT0utpyMAPx9tdqHzm2a-tS5ml76wy9CSshOynzkMzr5vBiko0A9qmn0fj91J-M7UzrooSpTt_bPvz_MaCdD4HDST5G_lUnD7l2qeRblcXsSJbzk5fv-5e11D2m_d41SriHYgzD4IKw5a3PLfGkMaCsqhXMmJGRd8SWIJI9PfgF2B0V7O_eF2R6ORnAmu4G2lOMVPpk-N-nJ2pF0PAOMyAyRGb7yNsyvjX2qQTOVjaa7z7AWEdIoeKuBW8jOyfEqtG2YxEO7w64vEdKuXeG8UbzlpeGRWdCCSfEf-KHFq2By7SxXOBcS8K5fvhqapc_r2s1KoQCHlEx70bcPd8vnO2yatBQWM5w2BdZQV9piW-GDtXWrNdkgsimEPTSpz6sSkY2Ur8M_r9bVn8AtIhthTAMGkQ1mKsNCcdlkgO0BMNfMHHDK-ItrsNCHf7aMv-CsKevTjgY-CuZbXRWalZjpoilB2b5_bv5hQDv3JbMunNH8PYa0ETLba5BdzWeQCpVXbkKo1vr7jqJP4euVs2Dc3arK4G_ggP2RzBDZnHx65_TwTuXYp4c3QPBLoTvZQifbUCcOKEYk3gz5snUDj0yxAjQiMa4ULquskeCsfhVuEvdZQG5hH1IYn3K4B34qAgedBu_O93bV3oDdty32fNJXXVFempnTuaBdmcanky4KcPAWdH9hQMM8I3GAWwmiJYqW5mi6i60WyrZp_MPlNSLJ2Uizn_vKWA2sbKt-hYWyXQ9I_rJkRuS34C0Mwpw7iK5RnDiEVxzSOKe3OOwa9SwKxeTvTGWyBZV8H0yHYgSTXEudZAkeAUIk-V7lkiwZQYouICUzSmJGaB-7MdotF6kLfDQWyu62u97Xktm80qWfHVsbFyIJ6Mx5GIWgoxBRnnAefDKEPWhg2VWEyDkYRZiOIwQJo5-MwMe-I-qWjnzPrnzHWfRV327pyHc8ygfI45y14jNVqWNZNQa7Z3tTt-U271P4-sDrK_Cjc_KiSk9LtkxozCvl-ltbrWebR8YPQsG9MlYjsnSTaVXJ1q5NSp9XMvPp7JtylHDuVBjJlFzKFLE4T1jw_y7TX167CXW0R7rMr3ThcfRVXf6shFpV9XEkxK8g6TicSLrOHlyRZJwlXyTpXoeHoX9V-uVBuJ29JNxYlkpYas2OO8hRtPpYjOju-0RwHEcihFciJBn9cgU06kn1ZIanplu7fp77xt12PM5Eb70cTbJFlM2jOZvAIowDQqM4SejksOAxm5OEczIDnobzPA_jIAqm82lCKQ1jOhELEpAoJGEURIRS6udZykge8JjROIlnCaIBlExI3xHwK11M2of6RTwl8WwiWQrStL8BEdKro6FgUlbcvadM1xO9aKmnTWEQDaQw1px9WWElLP7Htx_88wCq-yGnb1LuQVGos93w9JlNGi0XX39taUn-NwAA___Q8dHC">