<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/73599>73599</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [missing opt] redundant loads of variable addresses after a loop 
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          jnk0le
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/ab5bhT55P

It seems that after a loop llvm is forgetting that it ever loaded registers with some addresses.
Putting additional code in the loop bodies (e.g. increment volatile global) seem to not change anything.
Loop entered conditionally seem to not trigger this issue.


riscv32: redundant `lui`s everywhere

armv7a: `foo1()` has 3 redundand pc-rel constants for `a` address (5 total) , ` foo2()` and `foo3()` are fine

mips: even worser than riscv (due to zero offset loads/stores only in `foo2/3()`)

armv8a: everything is as it should be

x86-64: it really likes to spam 10/11 byte instructions everywhere (at -Os and -Oz of course)


GCC has this issue as well:
riscv32, arm32, arm64: only `foo1()` is fine


for reference here is a bit more real code that experienced this (requires stm32f0 headers):
```
void init_clocks()
{
        FLASH->ACR = FLASH_ACR_PRFTBE | (FLASH_ACR_LATENCY_Msk & (0b001 << FLASH_ACR_LATENCY_Pos)); // 1ws
        
        if((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL)
        {
                RCC->CFGR &= ~RCC_CFGR_SW_Msk; // switch to HSI (0b00)
                while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);
        }
        
        RCC->CR &= ~RCC_CR_PLLON;
        while((RCC->CR & RCC_CR_PLLRDY)); //!!! reload happens after this
        
        RCC->CFGR = RCC_CFGR_PLLMUL12 | (RCC->CFGR & ~RCC_CFGR_PLLMUL_Msk);
        
        RCC->CR |= RCC_CR_PLLON;
        while(!(RCC->CR & RCC_CR_PLLRDY)); //!!! reload happens after this
        
        RCC->CFGR = RCC_CFGR_SW_PLL | (RCC->CFGR & ~RCC_CFGR_SW_Msk);
        while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
}
```
</pre>
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