<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/73563>73563</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            lldb: CXXRecordDecl is incorrectly marked as trivial
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            lldb
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          hokein
      </td>
    </tr>
</table>

<pre>
    Split from the issue https://github.com/llvm/llvm-project/issues/72913.

```
// CXXRecordDecl emitted by clang is DefinitionData pass_in_registers aggregate standard_layout trivially_copyable literal has_constexpr_non_copy_move_ctor can_const_default_init
// CXXRecordDecl emitted by lldb is DefinitionData pass_in_registers aggregate standard_layout trivially_copyable pod trivial literal
struct NonTrivialCtor {
  int a = 0;
};
```

The synthetic CXXRecordDecl AST node in lldb is incorrectly marked as **trivial**, this will cause incorrect layout calculation.

[Comments](https://github.com/llvm/llvm-project/issues/72913#issuecomment-1822801804) from @Michael137 

> Something I noticed that makes this trickier is that RecordDecl::isTrivial() returns true for bar when using LLDBs AST. Whereas with clang it's actually false (which is correct because bar has a default member initialiser, making the default constructor non-trivial). This is important for mustSkipTailPadding, to determine whether to round up the size to alignment or not. So that's a separate bug that needs fixing first



</pre>
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