<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/73010>73010</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            ISel fails on Glue-edges with TableGen data
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          borisboesler
      </td>
    </tr>
</table>

<pre>
    I want to match the DAG `STORE((ADDC srca, srcb), dst)`. The currently
generated result is a machine instruction with *illegal* operands and
*without* the `Glue` edge from the `ADDC`. These might be two bugs.

TableGen generates the following code:

````
... // handling some STORE stuff snipped
/* 10235*/ /*SwitchOpcode*/ 70, TARGET_VAL(ISD::ADDC),// ->10308
/* 10238*/ OPC_RecordNode, // #1 = 'addc' glue output node
/* 10239*/ OPC_RecordChild0, // #1 = $srca
/* 10240*/    OPC_RecordChild1, // #2 = $srcb
/* 10241*/    OPC_CheckType, MVT::i32,
/* 10243*/ OPC_MoveParent,
/* 10244*/    OPC_RecordChild2, // #3 = $dst
/* 10245*/ OPC_Scope, 27, /*->10274*/ // 2 children in Scope
/* 10247*/ OPC_CheckChild2Type, MVT::i32,
/* 10249*/     OPC_CheckPredicate, 1, // Predicate_unindexedstore
/* 10251*/     OPC_CheckPredicate, 2, // Predicate_store
/* 10253*/     OPC_EmitMergeInputChains1_0,
/* 10254*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
/* 10257*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
/* 10260*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
/* 10263*/ OPC_MorphNodeTo0, TARGET_VAL(MYTGT::ADDC_xyz), 0|OPFL_Chain|OPFL_GlueOutput|OPFL_MemRefs,
                   6/*#Ops*/, 3, 1, 2, 4, 5, 6,
               // Src: (st (addc:{ *:[i32] } BRegs:{ *:[i32] }:$srca, BRegs:{ *:[i32] }:$srcb), ARegs:{ *:[i32] }:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 7
               // Dst: (ADDC_xyz ARegs:{ *:[i32] }:$dst, BRegs:{ *:[i32] }:$srca, BRegs:{ *:[i32] }:$srcb)
````

In `SelectionDAGISel.cpp` the node of operation `ADDC` is pushed to
`RecordedNodes` (offset 10238). When the node is morphed,
`RecordedNodes` has 8 elements (`store`, `addc`, `srca`, `srcb`, `dst`,
`zero_reg`, `zero_reg`, `zero_reg`), and the index computation to retrieve
the operands in this array ignore, that the node at offset 10238 was
recorded. Operands according to TableGen's list are `srcb`, `addc`, `srca`, `dst`, `zero_reg`, `zero_reg`,
which is wrong. Note, for `STORE((ADD srca, srcb), dst)` the
generated code is identical except the `OPC_RecordNode`.

It's unclear (to me), if table-gen should generate other indices
(`4, 2, 3, 5, 6, 7`), or if ISel should keep track of recorded nodes and recomputes
the indices.

When I modify the generated matcher and add the correct indices, ISel
morphs the `STORE` node into a machine-code node with the correct
operands, but fails to generate the outgoing `Glue`-edge.  As far as I
can see, the method `SelectionDAGISel::MorphNode()` is not able to add
the outgoing `Glue`-edge as an outgoing edge to the result.

</pre>
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