<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/72861>72861</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [GreedyRegAlloc][AArch64] The register allocation algorithm degrades the performance of unixbench's dhrystone subitems.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          XingYuShuai
      </td>
    </tr>
</table>

<pre>
    version: LLVM 18.0
source file: 
[src.zip](https://github.com/llvm/llvm-project/files/13414400/src.zip)

build command: 

1. clang -c -g -DTIME -Wall -pedantic -ansi -mcpu=tsv110  -DREG=register -DHZ= -O2 -fomit-frame-pointer -fforce-addr -ffast-math -Wall dhry_1.c -o dhry_1_reg.o
2. clang -c -g -DTIME -Wall -pedantic -ansi -mcpu=tsv110  -DREG=register -DHZ= -O2 -fomit-frame-pointer -fforce-addr -ffast-math -Wall dhry_2.c -o dhry_2_reg.o
3. clang -o a.out -g -DTIME -Wall -pedantic -ansi -mcpu=tsv110  -O2 -fomit-frame-pointer -fforce-addr -ffast-math -Wall dhry_1_reg.o dhry_2_reg.o

test command: ./a.out 10

result: 

By manually modifying the assembly file, the performance of the above applications can be improved.
Original Assembly File：
[dhry_1_reg.s.txt](https://github.com/llvm/llvm-project/files/13414602/dhry_1_reg.s.txt)

Manually modified assembly file：
[dhry_1_reg.s.change.txt](https://github.com/llvm/llvm-project/files/13414673/dhry_1_reg.s.change.txt)

Test results after manual compilation：


Analyze the log with debug-only=regalloc，you can get the machine IR of main fun. And you will find that the load instruction for the string constant @.str.4 is out of the loop:

However, the register allocation failure causes the preceding loop invariant extraction failure

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMlluP2ygUxz8NeUFYgHFiP-Qh0zRtpVaVutXeXiouxzYrDBbgTNNPv7I9M5vJXqTuttK-kNjgc_7n79_ByJRs5wH2qLpD1XEjp9yHuP_Z-u6X6Yd-knajgrnszxCTDR6VB_z27Y_vMKsLiugR0UMKU9SAW-tgnl1vououRV18sSOqjojXfc5jQuUB8RPip87mflKFDgPiJ-fOjz9kjOE30Bnx0xwuIX5ipWBCUIr46TEgbx5yLKOarDNYh2GQ3lwJWEZWYO2k7zDRmHSYHD--efcSk5-kc5iMYKTPVmMifbKYDHqcUHnM6cwYxZgcP7x8hcpjhM6mDBGT4-tfUXnE5D3HpA2DzaSNcgAyBuuXBW0bogYijVkuZMpkkLl_SGj6ePnECo1JePj_KUJXhFUq_99J5VdS-bXU8klqwLIIU_56wf_JwlXLXwhbxwwpXwNRIH5aZTJ6vS5Cmly-QoYzVN3ZQXbwL6GVKUGeqRVlI5pyxxA_wc6IZlsKYraaEaGkJooqQ1gF27ICVbfC3CB9d8GD9JN07oKHYGx7sb7DuQc8JxiUu6zdxl8sN0eIbYiD9BpwaNd1KpwBy3F0Vstsg09YS48VYDuMMZzBFGuq99F21kuHD4-RT3Pklyd09wI1h6dmvjI-Fflz_hZdvaUc8dOfIj_34t0zIyyYGw_-Wanupe_gmwnelbeCrxI81_1xhnAlLGHZzmyv73Qmc7RueSu36r8LgA0TkvGdIrtGtkRoJolsoCEUtq3Z1XVNW3Ejfh0PXrrLF1iAcqHD9zb32ICaOhK8u6z7jXQu6Ic66heXMC2gdZCXxwape-sBv_kwkzlI63E7-QIfvMHz2nvrHG6tNzj3Mj9kkgZbn3Kc9OwRbkNcJlKOcxvo4FOWPmMkaJFyLAS2Cc_d_cC-C2GcPfuOlm6bxrQ7UxNTM0FEJRmp50uuVFU2Qikm9Y2lr8M9nCE-9uzTTr34J9dCpXVTBKzllCCtrR1Bg5nLnqvC1p9ltHPx8DlHqa8fW9NszL40TdnIDezZjlJRi0rwTb8XpqWVKpWsYCdaSpXRZmt4zbaqpIayjd1zykvGOGVcNJQXqha0VKIp25YCbxskKAzSumI2qAix29iUJtjveL1lGycVuLScIjj3cI-XScT5fKiI-8VUNXUJCepsyumPKNlmtxw_XkUAc_kA3WFhqjqi6u5wiLrfClQd8ce_sU26LkSb-wEb6KI0j9Y93xUnbz8r8LpHfJeWT0fKwQNOk7IZhlRspuj2X03HUuVMx-LC7wEAAP__9Ejz-A">