<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/72743>72743</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SROA][X86] LLVM failed to merge two aligned i32 store into one i64 store
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          XChy
      </td>
    </tr>
</table>

<pre>
    Alive2 proof: https://alive2.llvm.org/ce/z/Wu8mZm
Missed example: https://godbolt.org/z/j6nE11szW
### Description:

SROA sometimes splits a large store into some independent stores, producing something like:
``` c
uint32_t* p = xxx;
uint64_t v = xxx;
*p = v
*(p + 1) = v >> 32
```
It can be transformed into a single i64 store:
```c
*((uint64_t*)p) = v
```

### Real-world motivation

This snippet of IR is derived from zstd/.../extr_zstd_compress.c_ZSTD_createCDict_advanced.c (after O3 pipeline).
The example above is a reduced version. If you're interested in the original suboptimal IR and optimal IR, see also:https://godbolt.org/z/erM1Tjx5G
And note that in the reduced version, the two loads in `src` are merged into one by X86 backend as expected.
But in original IR, the two i32 loads in `src` are still there:
```asm
76 mov     dword ptr [r13 + 8], ebx
77        mov     dword ptr [r13 + 12], r14d
```
In optimal `tgt` function, they are merged:
```asm
183        mov     qword ptr [r13 + 8], r14
```
So I tag X86 here.

**Let me know if you can confirm that it's an optimization opportunity, thanks.**
</pre>
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