<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/71883>71883</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            clang only sets `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16` on x86
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            clang
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          comex
      </td>
    </tr>
</table>

<pre>
    `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16` is a macro that's supposed to determine if the target has 128-bit compare-and-swap atomic operations.

But in Clang, this family of macros is defined on a target-by-target basis, and `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16` in particular is only defined on x86-64 (if the target has cmpxchg16b support), not any of the other targets that support 128-bit CAS.

This happens to affect part of LLVM's ThreadSanitizer runtime (`compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp`), which checks for `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16`.  If it's not set, then ThreadSanitizer implements 128-bit CAS [using non-atomic accesses under a lock](https://github.com/llvm/llvm-project/blob/5195d458587b02f3edf1347fae53417a74538648/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp#L157)... which can cause race conditions if instrumented code is linked with non-instrumented code.  (This risk is called out in a comment, but I find the design odd: if the target truly doesn't support 128-bit CAS, then why is it necessary to implement it for instrumented code at all?)

Anyway, I found four architectures (including x86-64) where Clang supports native 128-bit CAS.  This list may not be exhaustive.

| Target | To Enable | To Disable |
| - | - | - |
| x86-64 (X86) | `-march=x86-64-v2` | `-march=x86-64` |
| armv8 (AArch64) | (by default) | (n/a) |
| power64le (PowerPC) | `-mcpu=power10` | `-mcpu=powerpc64` |
| s390x (SystemZ) | (by default) | (n/a?) |

'To Enable' and 'To Disable' are example flags to target subarchtectures which do or don't natively support 128-bit compare-and-swap.  On all of these architectures, based on some [testing in Compiler Explorer](https://gcc.godbolt.org/z/sdWznG4bc), GCC defines `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16` iff there is native support.

Note however that "native support" is not the same thing as "implemented without calling a runtime function".

When the target truly doesn't have native support, GCC does not define `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16`, but still accepts calls to the relevant builtins, lowering them to runtime calls to functions roughly matching the builtin names.  For example, `__sync_val_compare_and_swap` with arguments of type `__int128` is lowered to a call to `__sync_val_compare_and_swap_16`.  Clang behaves similarly (though not identically).  However, this seems pretty useless.  Neither libgcc nor compiler-rt actually implements these functions, and they're not implemented by libc either.  Typically you'll just get a linker error.

On the other hand, when targeting base ARMv8 (e.g. `-march=armv8-a`), GCC uses runtime calls for CAS operations of all sizes, yet *does* define `__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16`.  However, the runtime functions used here are ARM-specific - e.g. `__aarch64_cas16_sync` - and *are* implemented in libgcc and compiler-rt.  And their purpose is different.  Even base ARMv8 supports compare-and-swap of all sizes, including 16 bytes, using a load-linked/store-conditional pair.  But ARMv8.1+ (specifically the LSE extension) adds instructions specifically for CAS, which I guess are preferable.  The `__aarch64_cas*` functions just choose between CAS instructions and load-linked/store-conditional depending on whether LSE is available; they don't use locks or anything like that.  I guess this is still native enough for the macros to be defined.  (Clang also implements this whole scheme, but, as mentioned, without defining the macro, regardless of the subtarget.)

</pre>
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