<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/71787>71787</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] The alignment of temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node is probably 8, not 4
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          twakatsuki
      </td>
    </tr>
</table>

<pre>
    The temporary stack introduced by the following patch causes a misalignment error when run on the Imperas OVPsim RISCV ISA simulator.

[RISCV] Use temporary stack in expanding SPLAT_VECTOR_SPLIT_I64_VL node
https://reviews.llvm.org/rG9d22b54d6b214e174b786316ccc9308aa7dd7be3

Example:
```
#include <riscv_vector.h>

int main() {
  size_t vl = __riscv_vsetvl_e64m1(1);
  vuint64m1_t x = __riscv_vmv_v_x_u64m1(0x8000000000000000ULL, vl);
  return 0;
}
```
Checked with the LLVM git main branch HEAD.
$ clang -v
clang version 18.0.0 (https://github.com/llvm/llvm-project.git b7b5907b56e98719b1dba8364ebcfb264fc09bfe)
$ clang --target=riscv32-kmc-elf -march=rv32gcv -mabi=ilp32d -S
```
main: # @main
# %bb.0:
        addi    sp, sp, -32
        sw      ra, 28(sp) # 4-byte Folded Spill
        sw      s0, 24(sp)                      # 4-byte Folded Spill
        addi    s0, sp, 32
        csrr    a0, vlenb
        slli    a0, a0, 1
        sub     sp, sp, a0
        li      a0, 0
        sw      a0, -16(s0)
        vsetivli        a1, 1, e64, m1, ta, ma
        sw      a1, -20(s0)
        lw      a2, -20(s0)
        lui     a1, 524288
        sw      a1, -24(s0)
        sw      a0, -28(s0)
        addi    a1, s0, -28
        vsetvli zero, a2, e64, m1, ta, ma
                                        # implicit-def: $v8
        vlse64.v        v8, (a1), zero
        csrr    a1, vlenb
        slli    a1, a1, 1
        sub     a1, s0, a1
        addi    a1, a1, -32
        vs1r.v  v8, (a1)
        addi    sp, s0, -32
        lw      ra, 28(sp)                      # 4-byte Folded Reload
        lw      s0, 24(sp)                      # 4-byte Folded Reload
        addi    sp, sp, 32
        ret
```
$ riscvOVPsimPlus.exe --version
20231024.0
$ riscvOVPsimPlus.exe --variant RV32GCV --trace --tracechange --program a.out
```
...
Info 'riscvOVPsim/cpu', 0x000000008000029a(main+24): 800005b7 lui     a1,0x80000
Info   a1 00000001 -> 80000000
Info 'riscvOVPsim/cpu', 0x000000008000029e(main+28): feb42423 sw      a1,-24(s0)
Info 'riscvOVPsim/cpu', 0x00000000800002a2(main+2c): fea42223 sw      a0,-28(s0)
Info 'riscvOVPsim/cpu', 0x00000000800002a6(main+30): fe440593 addi a1,s0,-28
Info   a1 80000000 -> 81ffffc4
Info 'riscvOVPsim/cpu', 0x00000000800002aa(main+34): 0d867057 vsetvli zero,a2,e64,m1,ta,ma
Info 'riscvOVPsim/cpu', 0x00000000800002ae(main+38): 0a05f407 vlse64.v v8,(a1),zero
Processor Exception (PC_PRX) Processor 'riscvOVPsim/cpu' 0x800002ae: 0a05f407 vlse64.v v8,(a1),zero
Processor Exception (PC_RAX) Misaligned 8-byte read from 0x81ffffc4
Processor Exception (PC_SED) NOTE: simulated exceptions are not enabled on processor riscvOVPsim/cpu
. If an application is being simulated that requires simulated exception support (to map memory on d
emand using an MMU, for example) please ensure simulated exceptions are enabled for correct behavior
...
```
Setting the stack alignment to 8 fixes the problem.
```
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 920657a198d9..7caa9483de6c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -92,7 +92,7 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {

       // Create temporary stack for each expanding node.
       SDValue StackSlot =
- CurDAG->CreateStackTemporary(TypeSize::Fixed(8), Align(4));
+ CurDAG->CreateStackTemporary(TypeSize::Fixed(8), Align(8));
       int FI = cast<FrameIndexSDNode>(StackSlot.getNode())->getIndex();
 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJysWFtz4joS_jXipcuULBtfHvJAIMxSlZyTCjmpfaNkuw3a8W0lmZDz67ck22AIqdmZOakUYLX63vrUba6U2FWId2R2T2bLCW_1vpZ3-p1_51q138UkqbOPu9c9gsayqSWXH6A0T7-DqLSsszbFDJIP0HuEvC6K-l1UO2i4TveQ8lahAg6lULwQu6rESgNKWUt432MFsq2grizvumxQcgV_vj0rUcLLerN4g_VmDkqUbcF1LaeELgmd95-ze7uFzJbwl7plHOCx4VVmrNk8P85ft28Pi9c_X7ab58f163Yd-Nu3R6jqDDuBe60bRbw5YSvCVhIPAt_VtCgO5bSWO7P0Lc4YS2Z-FiTM9dEN_SSMAs8N0jSNPRpxHmZZmKA3tvPhyMumQCO4Ww1o_989Mk9UadFmCMRbSKHSw_aAqfF2T7yHsSRRaSi5qAiLCIuBhPfdOoASf-NWw6EA4i1hu-3FKNSHYouBX7qERS5hMfFOPIdWVNqQthqOl3zlYXvYHrdtz0iPEb38--vxkbAFHIpLkRJ1KyugpyUSLm86vdhj-h0zeBd6b3P_-Pj2BDvR-QeJ5FW6h389zJdDypkPacGrHTiHbqV7OqBUoq7AjaZ0SoGw6DKLO6H3bTJN65KwlUll_-U0sv4PpnpqdCZhMotpmMwCjKPQjRM3S3jkBT4maZ6wwM9TGic5GmevrXE0lzvUxFva2HnM-V6mDhY5OCWX6d4QDh7bpQezkAjiLUXReCwDZ3MzNDbB3hwI84D41D4OhQKEzZJkSs-1RGOeZYLQWDUmId2n47ETWb0TGktulk3VRGZHbIX7TvKhEVZ1kWEGm0YUxSWXopbLP3Hd_PuRqME-erZvZF6qpDSbaFdOWCVnG4pCnEjdp3smtsmV05yeiCM-eulSt-i4gfGJnvNJY3NWxKHjdDtdbAEY-OartA_aRrHkVyItzWH0k8jCktmX5PasbMZ8FkW3BfufOMeudEm9IPcR7_jVadvY087Rv1HWNnTsB77ezvztWhBlU4hUaCfDvKtj_zBSXigM_OnB_IyMCsIiboGJLcDac10Z7teVYUlDti4rY-w8d2-Hpg_wqBoPypW3bLt91ug1e3HzrP2fp-YFi5pnl7J-9QReyboBESOrJeovLiYfLKZ19_Fz0aopHhEcpwfdbhujzHMp86c_ZuNS8ErDy5vHvi3eDHZKnuLwne55tTNPjax3kpfAp3V727TptL8W1lVeA2HhSCFhq7RpCQvt8T8ON5a9wVjMCYu6K_TehDU2FWpJsySEohU2oLYw-ktvpMcQoBfngkO8BxjuxV-0BkfWRL01OSY-85kH6h3O1nyCgZ_VZc74SVd60sV9xsa6qNUV_aau4KzLoyddvk9nsQemGjun1KDtKsZDVPsYu3me56n_i7aMMu4NGadZFIR0FkKPhdAjoQXCDgctDFoUHEDwpzWPsusN2aWcznKfhjAAIVioGaHgGQSfZZ2iUrWEh2OKjTZ9DmHR82L7_PJvgwbnDV-YBX0RG1v-MeUvc6v8qW_oMYOoAx-JPINc1qVRe5G0r4VtHpZG2B9_vj4YC_tOHzPAYaMCLhGqWgNWPCkwM-NCcxL42e0OIWCdA6-AN-Y24lajUJCgGQbOWvSea5D431ZIVLe0g2qbppbamKtrKHkDJZa1_DBW9AiLJa8yaJURzSt4evrLlENeS8C-9WcxNAVyhYCVaiV-7efgo-FOaykx1ZDgnh9ELa-w7woTN6i1scB0090AdJ63dA0R5OKIypIbWScFlrflZCLPwXFMX8xHPbNICFu9dr0uW3WDV_-93mCxnH97rZfzb9O0aSD5Nb5hyMnwCDGjwSzkbhxl8XQappzHfuRlGKTgUhr4fWE5jvOrVg631X33_3tGE58Sn4ITGwAJgbD74VdHONQi6wbagdfIMW28N3-W2JdzL_t6vLvowbqxBhYSuf4889qi4-l-NPma-XZ6IWKzfONFi7AxLJui1mb46-MJi1Yu598M8HYq7KbXQQ1h0etHgxvxN3bGr8QRM2J6166Fm5uaIyyySDuaDU2E_yHR0ZXo3iszHK_Wdo5NudLEW6wkL3Ftymmz_MNM-d4DYdHJ6-kOtV1mvURj2Q615egXTzqeeLoXFT7XotIo7VXw9Nxp-0zq7N-hti5YhYRFTyvjxWp9EZbh7E2yOy-LvZhP8M4N4njmxnQWTPZ3gRu7jAbhLPUjljMaB14Qpl6cBoHLc59PxJ3twFwa08gLvWCaUgwiP_OTLPESnyfEp1hyUZzeZEyEUi3ehW4YhZOCJ1go--6HsQrfwRIJY2S2nMg7Oysn7U4RnxZC6fP7kIkWurAvjU5vYV73OAKdOv-dVzIGrQ1O8aT4ANuNmyvAn7SyuPu5EZ-wlfVJEbayPv8vAAD__2PHXSU">