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<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/69785>69785</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[SROA] the limit on maximum number of alloca slices is too low for NVPTX (and, likely, AMDGPU).
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Artem-B
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</tr>
</table>
<pre>
e13e808283f7fd9e873ae922dd1ef61aeaa0eb4a added a limit on the number of alloca slices processed by SROA and set it to 1024.
The limit appears to be a bit too low for NVPTX, where we heavily rely on SROA to eliminate very expensive local loads/stores. The regression cases I'm aware of need it to be in the ballpark of 2K.
Based on the comments in the code review, bumping the default to that value may be a bit too much for rust. We may need to figure out how to make the threshold default target-specific.
For CUDA I could change the default by making clang driver pass the new threshold via additional cc1 options, but it would not work for JIT users using NVPTX back-end.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJx0U0-v4zQQ_zTuZdQocdq0OeTQt1XRAwEreAtcJ_YkMXXiyGO322-P7D5YnhCXxIln5vdH80NmMy5Endi_iP15gzFMzncnH2jevmx6px8dVTUdy6M81sNh0C0dDzVSK6XWFQ1NhYRYUr9DQK1JA4I1swngFggTwRLnnjy4AdBapxDYGkUMq3eKmElD_4Bff_n5BLhoYApgAgQHVSl3hSjPojw9n28TvU_GdSX0nKp6AoQ-dziw7g6D8_DTb5_f_hDyE9wn8gR3gonwZuwDPNlHIpbxggNKAxcMBDfyD6CvKy1sbgSJqQXrULOQFw7OExeQKHgaPTEbt4BCJoZXIQ8z4B09JZULkX6X0BOYpwk9Wruiv6YC-cMHWS-YPHg3S7l5piXw333K6YR4M3RPevo4r2YZ85WmAaPNOGHCADe0kWDGx0dP5qimbIqPHAr4_VmSSQYHgxljoh0DTO6e_sx4pTw_TJ54clZ_Q0I_UtjySsoMRn1QcXEePn05n-AVlItWg5pwGekD0_6Rpif-yuIygvbmRh5WZH5uCt3_hXozeaFMMG5BC0pV4Nb0wU8n8p7cM9bi0slfs87vX98gMnmGyAkrLwP0qK5bWnSx0V2t27rFDXVV0x6O9aHdl5up26M61GWjZU37sm2GIzaNVH3TYtmo3a7ZmE6Wsq5KWcqqbquy6Hf1oTk0VNXHsqz7WuxKmtHYwtrbXDg_bgxzpC6h7DcWe7KccyZlkpovhZQpdr5LPds-jix2pTUc-NuUYILNAU1bK_bnbNY_GZvxq5nj_L85M_zfbICQR1x0MtKaK9lHOp1-PH_3-YuQbbGJ3nZTCCuL-iTkRcjLaMIU-0K5WchLYvb-2q7e_UkqCHnJelJast6_AgAA__-oFXMb">