<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/68783>68783</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [PowerPC] Incorrect and/anyext interchange in custom combine
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:PowerPC,
            miscompilation
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            nikic
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          nikic
      </td>
    </tr>
</table>

<pre>
    ```llvm
; RUN: llc -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s
define void @test(i32 %x, ptr %p) {
  %lshr = lshr i32 %x, 1
 %zext = zext i32 %lshr to i48
  %and = and i48 %zext, 255
  store i48 %and, ptr %p
  ret void
}
```
Results in:
```
        rlwinm r3, r3, 31, 24, 31
        stw r3, 0(r4)
        blr
```
Note the missing store of the upper 16 bits.

This is caused by an incorrect custom DAGCombine added in https://github.com/llvm/llvm-project/commit/b0e249d5e289dc3f7e4a7cff785453206925f8b9.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUU81u8ygUfRq8QY4wmNheeJEmymg2VVXNPADg65gpBgtw087TjyB2p5_UzSdZcAznXu65PyIEfbMAPeJPiFKr37RClCJ-KcQaJ-f7fFRIN3z26EgenzHvMyIXRE6IPeHXv58RO2FjFC7n6PViALHL4u7gF3WsDZSrfbPubvcdl8uiShHmclyNKT3cSitmCBixM0aUh4fvAUZtAb87PWBUkwghItpqRhPnA9EzXqJPeEG0w6h5epjhdGTC5DFiF5zBd5tqYyHK_4WPmEkZbKRsEB3WdfvNn7BDZqZd1-1unRxSzndiiM7Dfi_s8EuMG8dDzJK2_DWXDey5ffy-QlhNDFhbxE4_MhDpvLlrO2PP0juPlVU5pHrDOzPE-0YgiLa-RrT7upPG__jAs4uA4wR41iFoe9vUuTEfrssCHldHLHUMh91ZWv-adMA6YCXWAAOWn1hYrK1y3oOKWK0huhlfTn-c3SxTgcUwwIC1xVOMS0h66RXR603HaZUH5WZEr7njHlu5ePcPqIjoVbl51glIArTuBg607QbFxgZq0ahxbFpec0bJsaN8bGV3KIaeDR3rRAF9dewaUnVVVxdTL3nNu7ZpBQBpGjkCdFzIShJes2OlWKF7SiirSFVVpGJVfRADAJFcsrFqRtaMqCYwC20OKciD87dCh7BCf2yblhVGSDBhGzMp1BvYAbHTS5qSl3MaOZrWWQfl5kUbEbWz2yT6PuuW6y2gmhgdYvj_kaijyeO7u-IX_OdXtnMTXoX9zB1uI3g1CXuDlO6tEupRhmL1pv_tCmSJAdFrVvlfAAAA__9caEdl">