<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/67843>67843</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Missed optimization
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ojeda
      </td>
    </tr>
</table>

<pre>
    From: https://github.com/rust-lang/rust/issues/116272

```llvm
@switch.table.src = private unnamed_addr constant [3 x i32] [i32 255, i32 0, i32 1], align 4

define i32 @src(i8) {
  %switch.tableidx = add i8 %0, 1
  %2 = sext i8 %switch.tableidx to i64
  %switch.gep = getelementptr inbounds [3 x i32], ptr @switch.table.src, i64 0, i64 %2
  %switch.load = load i32, ptr %switch.gep, align 4
  ret i32 %switch.load
}

define i32 @tgt(i8) {
%_2 = zext i8 %0 to i32
  ret i32 %_2
}
```

https://alive2.llvm.org/ce/z/rjWCBw
</pre>
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