<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/67596>67596</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Inline assembly needs to accept RISC-V Vector `vl` register as clobberable for GCC compatibility
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          sh1boot
      </td>
    </tr>
</table>

<pre>
    GCC for RISC-V supports a `vl` register in its clobber list, so it knows when the assembly contains `vsetvli` or similar. Clang seems to assume it's clobbered, but since it doesn't accept the name in the clobber list it's not source-level compatible.

https://godbolt.org/z/Ecf3q64qP
</pre>
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