<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/66467>66467</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            The Union type affects the elimination of redundant memory access.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          vfdff
      </td>
    </tr>
</table>

<pre>
    * test: https://gcc.godbolt.org/z/7ebq45TMx

* when we defined the type __m256 with a union type
```
typedef union {
     fvec32 vect_f32;
} __m256, __m256d;

FORCE_INLINE __m256 _mm256_loadu_ps(float const * mem_addr)
{
    __m256 res;
    res.vect_f32 = svld1_f32(svptrue_b32(), mem_addr);
    return res;
}

FORCE_INLINE __m256 _mm256_mul_ps(__m256 a, __m256 b)
{
    __m256 res;
    res.vect_f32 = svmul_f32_z(svptrue_b32(), a.vect_f32, b.vect_f32);
    return res;
}

__m256 calculate(__m256 a, __m256 b) {
    return _mm256_mul_ps(a, b);
}
```
 we'll get it assemble with 2 memory load **ld1w**
```
calculate(__m256, __m256):                  // @calculate(__m256, __m256)
        ptrue   p0.s
        ld1w    { z0.s }, p0/z, [x0]
        ld1w    { z1.s }, p0/z, [x1]
        fmul    z0.s, z1.s, z0.s
        st1w    { z0.s }, p0, [x8]
        ret
```

*  then, if we defined it typedef svfloat32_t __m256; （**change the #if 1 to #if 0 in line 21**）
```
FORCE_INLINE __m256 _mm256_loadu_ps(float const * mem_addr)
{
     __m256 res;
     res = svld1_f32(svptrue_b32(), mem_addr);
     return res;
}

FORCE_INLINE __m256 _mm256_mul_ps(__m256 a, __m256 b)
{
     __m256 res;
     res = svmul_f32_z(svptrue_b32(), a, b);
     return res;
}

__m256 calculate(__m256 a, __m256 b) {
    return _mm256_mul_ps(a, b);
}
```
we can have efficient assemble 
```
calculate(__SVFloat32_t, __SVFloat32_t): // @calculate(__SVFloat32_t, __SVFloat32_t)
        fmul    z0.s, z0.s, z1.s
        ret
```
</pre>
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