<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/66261>66261</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPIRV] SPIR-V module layout doesn't respect the spec.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:SPIR-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            Keenuts
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Keenuts
      </td>
    </tr>
</table>

<pre>
    The layout of a SPIR-V module is very strict (https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_logical_layout_of_a_module).

Example:
 - An OpVariable instruction cannot be present outside of the first block of a function.

As-is, the backend doesn't respect those rules, but lower IR instructions to SPIR-V in place.
This means the following LLVM IR won't build to a valid SPIR-V module:

```ll
define void @main() #1 {
entry:
  %0 = alloca <2 x i32>, align 4
  %1 = getelementptr <2 x i32>, ptr %0, i32 0, i32 0
  %2 = alloca float, align 4
  ret void
}

attributes #1 = { "hlsl.numthreads"="4,8,16" "hlsl.shader"="compute" }
```
</pre>
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