<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/65722>65722</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [ARM] Compiler -S output for MVE uses .cpu .fpu directives that do not include MVE, leading to failed assembly 
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:ARM,
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          smithp35
      </td>
    </tr>
</table>

<pre>
    The following C example at -O2 uses MVE instructions with -mcpu=cortex-m85+fp+mve -mfloat-abi=hard
```
#define DUMMY_CONST_1 (0.0012345F)
#define DUMMY_CONST_2 (0.01F)
#define DUMMY_CONST_3 (0.02F)
#define DUMMY_CONST_4 (0.03F)
#define DUMMY_CONST_5 (0.04F)

typedef struct
{
    float a;
    float b;
    float c;
    float d;
} dummy_t;

int8_t foo(dummy_t *handle)
{
    handle->a += DUMMY_CONST_2 * (DUMMY_CONST_1 - handle->a);
    handle->b += DUMMY_CONST_3 * (DUMMY_CONST_1 - handle->b);
    handle->c += DUMMY_CONST_4 * (DUMMY_CONST_1 - handle->c);
    handle->d += DUMMY_CONST_5 * (DUMMY_CONST_1 - handle->d);
    return 0;
}
```
The program compiles to an object file and produces assembly with -S (trimmed)
```
        .text
 .syntax unified
        .eabi_attribute 67, "2.09"      @ Tag_conformance
        .cpu    cortex-m85
        .eabi_attribute 6, 21   @ Tag_CPU_arch
        .eabi_attribute 7, 77   @ Tag_CPU_arch_profile
        .eabi_attribute 8, 0    @ Tag_ARM_ISA_use
 .eabi_attribute 9, 3    @ Tag_THUMB_ISA_use
        .fpu fpv5-d16
        ...
        foo:
        .fnstart
 .cfi_sections .debug_frame
        .cfi_startproc
@ %bb.0:
 movw    r1, #52978
        vldrw.u32       q1, [r0]
        movt    r1, #15009
        vdup.32 q0, r1
        mov     r1, r0
        adr r0, .LCPI0_0
        vldrw.u32       q2, [r0]
        movs    r0, #0
        vsub.f32        q0, q0, q1
        vfma.f32        q1, q0, q2
        vstrw.32        q1, [r1]
        bx      lr
 .p2align        4
@ %bb.1:
.LCPI0_0:
        .long   0x3c23d70a @ float 0.00999999977
        .long   0x3ca3d70a @ float 0.0199999996
        .long   0x3cf5c28f @ float 0.0299999993
        .long   0x3d23d70a @ float 0.0399999991
```

The important parts are 
```
.cpu cortex-m85
.fpu    fpv5-d16
```
Which do not include MVE. When assembling the file we get the following error messages:
```
t.s:48:2: error: invalid instruction, any one of the following would fix this:
 vsub.f32        q0, q0, q1
        ^
t.s:48:6: note: invalid operand for instruction
        vsub.f32        q0, q0, q1
 ^
t.s:48:2: note: instruction requires: mve.fp
        vsub.f32 q0, q0, q1
        ^
t.s:49:2: error: instruction requires: mve.fp
 vfma.f32        q1, q0, q2
        ^
```

If I comment out the directives so that the assembler relies on the -mcpu then it assembles correctly.

Glancing at the code I don't think that there is a .cpu and .fpu combination or .arch_feature that supports MVE so I don't know what we would put in its place as of LLVM 17.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUV19zm7oT_TTyy44ZkIzBD35w4ub3y0xz22nTdu6TR6DF1i1IVBJ28u3vCIj_YJLcZDI2FuecXVa7q4VbK7cKcUniGxKvJ7xxO22WtpJuV7N4kmnxvHzcIRS6LPVBqi3cAj7xqi4RuIPpFwqNRQsPPz-BVNaZJndSKwsH6XYwrfK6IWyda-PwaVqlMaE3RU3oTbVHmFZFqbmb8kwStt5xI0i4JuGKzMP-v_tJmcBCKoT1j4eHvze3X_76_riJgNA0DMIwomwW3xG6eAtNe3T0HpD1QPoecNYD2XvAuAfOzoDtp3uuUWABXdD6O8lNdwEA0EYHOGFXa9nIWj6yJo5rJFmDaKrqeeNOa-2nVC7dOCi0JjTtIUDoaseVKPHk87ln3b0pYZ84EHpD2Poq2iv_2JcbNj3neWE2KpmNSbL3JbPXJfMxydn7kvnrkmJMMn5fUgwlDbrGKAjPt2q0DnwZ1kZvDa8g11UtS7TgNHAFOvsHcweF9FWphIeJJkcL3FqssvK5L8fv3jdnZFWhOO3spRno_wKHT31WQmCfleNP0ChZSBQDIPJMbrhzRmaNQ5gnhN4CoZQG4YJQ2qHILIRHvt3kWhXaVFzlOJDJ68Z_n_WKt814KzQ6k779-mPDTb57m9d6lyQjvE1ttA_h2_zU88PzR1p9e9jcf19tGvtCHXIWnsPOOY____FwM2C9GCzqBop6H09FNB_cCoLLBV-1bDXkK-u4Oe5dXsiNxb4tBwKzZrspDK-u4u9xnlgbnfepMQuB0DjLgvBkptL7Q5u4UbfPLKaLJL0U25fCHIKG9ZsPfzpsfGNCEq8vsZXeuwu9KA7DxUBPNHXAKPwJPcZEVwpwUjCDRObC-DV6C8Hn26_34SZ8x1f6pq-2tRT2vg61bJMFxVGq97f_HHi9Lyp-gY3OsHSo68whGGK9j9GVj9lT912alwyoKS_lVr0AZsPNjY6be4zQVVKVWm0BIHxiOWUiCXmbyt0x44_hRfeXJK_z-Agv6nnDRD-jFXFO0-KSRnsae5UmxrxkPS0aHzSObVZWtTaOKwc1N84CNwijlLZpDTtWW8C-OC9qeMD8tZP5DoQGpR1IlZeNQD9FBfBrh-qlcfuBy_nxy3f2A8IWXff7OI6hMdpAhdbyLdrjvg2sucDfmqWErShhq47lL6Ta81KK89nNZxZXz6AVgi4G5g66KQUU8gncTp7MfSjxSfzpyqu5d0Zph-dO6RqNP84KbS4c_HjJjZmklyaP8mDwTyNNG0yo9hgU9SsWP_KQi5HQ_weTH2kSR5OjeX1fwL2fGypUDnTT5ZGQxp8Me7RgNbgd75b77EMDBkuJFrRq19t53l8pkO6Isr4CvE75HJxb_F_JVe6TplfNtUC4B-FTLPFLUv0-2jQI0gLvxgC_6W0V5brKpOJtjLSBoD2mC-SuMdhRbVP7Wu3eQKw-0_-t9AEOHnPAPm_rxtcaSGehLnnuH9Sn-OfPPx8gSoKJWDKxYAs-wWU0X8yieZhGyWS3TGORZylmKS-iJIvTNEGaMJYKztiCp_OJXNKQsnARpmEaMZYEc5ElLBTzcIYpxRTJLMSKyzIoy30VaLOdSGsbXM7jhNJJyTMsbfsSRmnG89-oBGGr1bcHQv1pRChVeICW4lfi9cQsvdI0a7aWzMJSWmdP2k66sn2n8wrxGm67cdH4CVA3zofB15QPWfv21ga9DfhZQrThvW5QPvNK5KJtTRoKLksUp0Fz0phyuXOubpuDf42620q3a7Ig1xWhd97H_mtaG-3nVkLv2iezhN618fg3AAD__8s7EPY">