<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/65109>65109</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Arm integer fetch_add(relaxed) that discards results should use zero register for output operand of ldadd
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          gonzalobg
      </td>
    </tr>
</table>

<pre>
    The code generation for: 

```c++
#include <atomic>
void add(std::atomic<int>& v) {
 v.fetch_add(1, std::memory_order_relaxed);
}
```

for Arm v8.4+ is:

```asm
ldadd   w8, w8, [x0]
```

The value written by `ldadd` to the destination operand is never read-from, and codegen should instead be: 

```asm
ldadd   zr, w8, [x0]
```

**Note**: this optimization is - in general - unsound for `ldadda` since that'd drop the acquire, i.e., `v.fetch_add(memory_order_acquire);` cannot be optimized to `ldadda   zr, w8, [x0]`.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUU02P4ygQ_TX4UopF8Efsgw9J9-a4p723MFRsVhiyUE5359evsJN098z0SCMhbAFV9d6rVzJGMzjEjlUHVj1ncqbRh27w7iqt74es9_q9-2dEUF4jDOgwSDLewckHVuyB8WfG97e95utSTBzSWk9FYZyys0ZgxZMkPxnFir_Wy4s3GqTWTDSRNCv2rNjfnzwZR-mhqOHCRAtsd8sIl_yEpMaXNXDLxBM8oiecfHh_8UFjeAlo5RtqJlpW3OHsnn9A-5nCyQfYhwkuTV4ycQATU9ZfcZRxWk-slloDwGuTcKw7qw5vnFW_q5Q0vUg7I7wGQ4QO-ndgNV_SsZoDeaARQWMk41bN_RmDdBpMBIcXDBBQ6s0p-CkVTTepSwM6iKOfrQbjIqHU0OO3vfqJxzX8EQ8m0vrbE65_qRCNJoI_k5nMdUVuImzAuJuBLGxgdtHPTicfPWjLxDsapxBolMTEToMO_rwIIdV_swmYYJkc8wVezb9a4UvzHwFL82sOSjrnCXq8Y0OdVH5U_458zfNMd4Vui1Zm2G3rtijauiqrbOx2qixlsaux3DZtz5XSqqh6LE-NlLtWtpnpBBcFbwq-3VZVWeVtUyrZNFuNZV_XqmElx0kam1t7mXIfhszEOGNXV1veZlb2aOMynkI4fIXlkgmRpjV0KWbTz0NkJbcmUvzIQoYsdsnMxhEOGOCzUh-TsUgN2kQlg44QMM6W4t1Bc0S4YvAQcDCRUhYfwM90nunhR3-CRcFsDrYbic7L1IgjE8fB0Dj3uUoWPSZst8_mHPy_qIiJ48IoMnFcGP8fAAD__3NVYcg">