<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/64954>64954</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            ARM vld1/vst1 codegen
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          psiha
      </td>
    </tr>
</table>

<pre>
    Unnecessary register moves get generated for custom memcpy-like function for aarch32 (and perhaps the scheduling could be better i.e. grouping more loads together)
https://godbolt.org/z/YdWosrs3e
</pre>
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