<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/64884>64884</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            copysign of select derived from sign comparison can fold into sign operand
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:optimizations,
            missed-optimization,
            floating-point
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    This can be folded to better use the sign argument to copysign 
```
float copysign_conditional(bool cond, float x, float val) {
    return __builtin_copysignf(val, cond && x < 0.0f ? -1.0f : 1.0f);
}

```

Produces this IR:
```
define dso_local float @copysign_conditional(i1 noundef zeroext %0, float noundef %1, float noundef %2) local_unnamed_addr #0 {
  %4 = fcmp olt float %1, 0.000000e+00
  %5 = and i1 %4, %0
  %6 = select i1 %5, float -1.000000e+00, float 1.000000e+00
  %7 = tail call float @llvm.copysign.f32(float %2, float %6)
  ret float %7
}

```
This can be optimized to:
```
define dso_local float @copysign_conditional(i1 noundef zeroext %0, float noundef %1, float noundef %2) local_unnamed_addr #0 {
  %4 = select i1 %0, float %1, float 1.000000e+00
  %5 = tail call float @llvm.copysign.f32(float %2, float %4)
  ret float %5
}
```


Pattern appears here: https://github.com/RadeonOpenCompute/ROCm-Device-Libs/blob/46939af92ad91238c878a82aad2220822073ffa1/ocml/src/powF_base.h#L68
</pre>
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