<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/64794>64794</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[MIPS] miscompile of 64-bit shift with masked shift amount
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
jacobly0
</td>
</tr>
</table>
<pre>
```llvm
target triple = "mips"
define i64 @f(i64 %0) {
%2 = and i64 %0, 63
%3 = lshr i64 -1, %2
ret i64 %3
}
define i32 @main() {
%1 = call i64 @f(i64 12)
%2 = icmp ne i64 %1, lshr (i64 -1, i64 12)
%3 = zext i1 %2 to i32
ret i32 %3
}
```
`version 16.0.0 (https://github.com/llvm/llvm-project.git 08d094a0e457360ad8b94b017d2dc277e697ca76)` returns 0
`version 17.x (https://github.com/llvm/llvm-project.git 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8)` returns 1
```diff
andi $1, $5, 63
addiu $2, $zero, -1
- srlv $2, $2, $1
- not $1, $1
- addiu $3, $zero, -2
- sllv $1, $3, $1
- or $3, $1, $2
+ srlv $3, $2, $1
andi $1, $5, 32
- movn $3, $2, $1
+ move $2, $3
jr $ra
movn $2, $zero, $1
```
</pre>
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