<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/64591>64591</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AMDGPUCodeGenPrepare should stop promoting uniform i16 values
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    With DAG divergence and RegBankSelect, theoretically codegen should now have enough information to handle promotion of uniform 16-bit ops directly. This was originally done as a workaround for having no uniformity info after the IR.

AMDGPUCodeGenPrepare awkwardly uses forward iteration, which just so happens to work around a defect in uniformity info where newly created values are assumed uniform. I currently have a problem that requires iterating in reverse like a normal combiner, and this is blocking the reversal
</pre>
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