<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/64104>64104</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            arm64: illegal asm generated for NEON `vfmlalq_laneq_*_f16` intrinsics, 3rd operand must be among v0..v15, cannot be v16..v31
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          bjacob
      </td>
    </tr>
</table>

<pre>
    The `vfmlalq_laneq_low_f16` and `vfmlalq_laneq_high_f16` intrinsics are meant to lower to `FMLAL`, `FMLAL2` instructions:
https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16

These `FMLAL`, `FMLAL2` instruction have 3 NEON register operands, the 3rd of which is encoded on only 4 bits instead of the usual 5 bits, restricting it to be a register among `v0`, ... , `v15`:

https://developer.arm.com/documentation/ddi0596/2021-03/SIMD-FP-Instructions/FMLAL--FMLAL2--vector---Floating-point-fused-Multiply-Add-Long-to-accumulator--vector--?lang=en

This is more explicitly stated in the Arm Architecture Reference Manual, C7.2.123 FMLAL, FMLAL2 (by element):

```
Decode for this encoding
 if !HaveFP16MulNoRoundingToFP32Ext() then UNDEFINED;
 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt('0':Rm); // Vm can only be in bottom 16 registers. 
```

This testcase shows Clang illegally generating assembly with these instructions trying to use registers outside of the allowed range for this 3rd operand:
https://godbolt.org/z/fsbKGMqWx

Recording this in a GitHub gist to make this GitHub-self-contained:
https://gist.github.com/bjacob/139a6b995f5328878527acb59ed667f0
</pre>
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